Loading...

Follow Verification Excellence on Feedspot

Continue with Google
Continue with Facebook
or

Valid

In SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range. 

For eg: consider  a 2 bit variable declared as     randc bit [1:0] y;

Every time this variable is randomized,  the values are iterated over the possible range (in this case 0,1,2,3)  and no value will be repeated until the range is completely iterated. 

One common questions asked in interviews is to implement this behavior without using randc variables.

Here is one implementation that I can think off .  The example shows a “N”  bit vector  which is randomized.   The concept is simple.  Each time a value is generated, it is maintained in a list and the next generation picks a unique value for the variable which does not match the existing list.   The list is then deleted once the maximum number of possible values are generated  which mimics the completion of one iteration of randc variable.

module test;
  parameter N =10; 
  typedef bit[N-1:0] my_type;
  my_type randc_var;
  my_type gen_done[$];
  function automatic my_type get_randc();
    bit succ =0;
    while(!succ) begin
      succ =  std::randomize(randc_var) with 
{ unique {randc_var,gen_done};}; end //If success push to queue gen_done.push_back(randc_var); if(gen_done.size() == 2**N) begin gen_done.delete(); end return randc_var; endfunction initial begin for (int i=0; i <1000; i++) begin $display("randc[%0d] = %0d", i, get_randc()); end end endmodule

A follow on question  for above code:  Why  is there a  need for automatic function? 

Alternatively you can implement the same using   a  rand  variable inside a class and writing a similar constraint  as part of the class.   In that case,  you can push the randomized value into the list  in the post_randomize() function.   And once the  list reaches maximum possible values, the list can be deleted so that iterating over values starts again

class  randc_test;
  parameter N =10; 
  typedef bit[N-1:0] my_type;
  my_type randc_var;
  my_type gen_done[$]; //queue of items done
  constraint randc_var_c {  unique {randc_var,gen_done};};

  function void post_randomize();
    gen_done.push_back(randc_var);
    if(gen_done.size() == 2**N) begin
      gen_done.delete();
    end  
   endfunction
 endclass 

The post Implementing randc behavior using regular constraints in SystemVerilog appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

What is a Verification Test plan? What are details to be included in a Test plan? Why is it important in functional Verification? What are some sample test plan templates? How is a Verification Test plan used and helpful?

Design Specification

A design specification (also known Architecture/ Micro architecture Specification) is a document that is developed by an architect or micro-architect capturing all the details of a design and its implementation. This would include all the supported features, interfaces and protocols , configuration and initialization information including registers, and other details. A verification engineer who is responsible for verifying a given design considers the design specification as a golden reference. His job is to make sure that the design implementation is functionally correct with respect to this design specification.

Verification Test Plan

A Verification Test plan is a specification document that captures all the details needed for verifying a given design. A Verification engineer is responsible for developing this plan initially as he understands the details of the DUT (Design under Test). A proper planning is always important to complete verification with highest quality and in a predictable time period

By failing to prepare you are preparing to fail

– Benjamin Franklin

Many a times if you don’t give enough importance to this, you are setting yourself to failures later in the project – which can include bug escapes, re-working several infrastructure work, time crunches, and loosing on quality.

What all details should be included in a Verification plan?

The Verification plan should cover all aspects to ensure a quality verification in a predictable time. I would break this into following categories – What to Verify ? How to Verify ? When to Verify ? How to ensure completeness with quality ?

What to Verify ?

The plan should list down details on what all features of design to be verified. A brief explanation of all features should be listed as individual test plan items. In addition to the features, all supported design configurations (register settings) under which these features should be tested should be listed down as test plan items.

Not all of these features/configurations will need individual tests. Most of the times several of these features and configurations needs to be tested in combination. A good constrained random verification infrastructure will be designed with this in mind. Details on stimulus infrastructure should be included accordingly.

In addition to the features and combinations, it is good to capture specific micro-architectural cases that needs to be ensured for correctness. This could include explicitly calling out cases for individual test scenarios or coverage observation. Some examples of this include various interface properties and internal micro-architectural events ( like state machines, fifos, arbitration and other logical block interactions).

Another category of what to verify also includes specific stimulus patterns, interactions, high level usage scenarios, potential deadlock/livelock conditions etc – some of which depends on the type of design.

This section should finally translate to a good quality stimulus and coverage properties that can ensure the quality of stimulus.

How to Verify ? 

Once details on what to be verified is understood and capture in the verification test plan, next step is to figure out how best each of the items can be verified. Based on the type of design and what needs to be verified , different set of methodologies, different types of stimulus , different type of checking mechanisms etc would need to be designed and implemented.

Majority of functional verification uses simulation and constrained random / coverage driven approach for faster verification. Selective areas of design and special features could also be tested using formal verification or other techniques. Details about how the stimulus infrastructure will be developed, the various knobs to control randomization for better coverage, development of sequences and tests etc should be in this section.

Checking mechanisms to ensure functional correctness should also be designed and captured in the verification test plan. Checks could be implemented as scoreboards, interface or embedded assertions inside RTL or verification components.

Both details on What to verify and How to verify are necessary to architect a good verification test bench and this should be documented in the test plan itself. A block diagram of various test bench components, hierarchy and stimulus patterns should be captured and explained well so that this can be translated into implementation with lesser issues later in the execution.

When to Verify ?

Every project has a time line for completion and as a matter of fact, there will always be more things to be verified in lesser time. The verification test plan should capture a rough effort estimate for a complete execution – in terms of time needed for development of verification test bench components, stimulus patterns, testing and regressing, coverage analysis, debug and quality completion.

Based on the effort estimate, it is a common practice to also classify the various features/configurations to be verified into at least three priorities (say High, Medium, Low). This helps in making better calls during project execution timeline to prioritize and de-prioritize various task and make informed decisions.

Reviews

Not all need to be perfect while developing a verification test plan, but it is still an important document to be made upfront when a design verification needs to start. Most of current design life cycles see several changes through development and the verification test plan will need updates as well. Another good practice seen is to review the verification test plan at least 3 times in a project life cycle – once in beginning, middle and towards end. This is collectively done with verification and design engineers along with architects and other experts.

The post What is a Verification Test plan ? appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

An ASIC or SOC Verification job is increasingly becoming like a Software coding and debugging profile.

However what is different is that you also need to be thinking like a hardware engineer while you apply some of the software engineering practices in coding and debug.

Most of Verification infrastructure (test bench, stimulus generation, build, regression, triage) all needs coding.

Most of current complex designs are functionally verified using simulation and the test bench infrastructure is coded usingobject oriented programming concepts. SystemVerilog language and the UVM base class (and methodology) all heavily uses the same.

Most companies have emphasis on coding guidelines, reviews and best practices just like software development. You will also need to be familiar with version control systems (CVS, Perforce, Git etc) to good extend

Most of designs and the verification infrastructure are complex and developed by small to big teams – and practices likecontinuous integration for builds and release are adopted by Verification engineers just like Software engineers(e.g Jenkins)

There is a lot of scope ofautomation of routine jobs of verification engineer – and scripting languages like Python/Perl are heavily used. (regressions, triage, machine pool management etc)

Verification engineers also spend a considerable time in debug of their own code as well as the RTL (model of hardware design). This is where you will need to understand code that looks like software (Verification code) as well as think like a hardware engineer (looking at RTL and simulation wave forms)

With all that said, it is fun , lot of challenges and learning !

The post How similar is an ASIC verification job compared to a Software coding profile? appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

There are mainly two types of companies in the VLSI/Semiconductor industry. Quite often entry level engineers gets confused between these and wonder what are the differences and which one is better in terms of career.    Here are some details which hopefully will give you some insights.

Product Companies :

The companies designs and develops products for one or more applications focusing one or more markets. The product could be a single chip (ASIC/SOC) or a platform solution with multiple chips and associated software. These companies work on end to end design life cycle.  i.e  starting from identifying market opportunities and designing solutions using hardware and software,  developing the hardware and software, testing and validating the product, marketing and supporting customer deployments.

Pick any big names like Intel,Qualcomm, Nvidia, AMD, Broadcom, Samsung, NXP, Mediatek, TI, Analog Devices, Micron, etc – all of these fall under this category.  All of them would be developing products for one or more market segments and constantly trying to innovate on their products.

Additionally there are  several startups that also gets founded with a vision and focus on developing products, especially in niche markets.  You could find several of those  in trending/upcoming fields like Artificial Intelligence, Machine Learning, RISC-V based processors, storage and new memory technologies etc

The advantages of working in a product companies comes with exposure to entire product development life cycle. There would be engineers with varied skills working together with an end goal of developing and deploying products and solutions.  As an employee, you can gain significant domain knowledge in a certain market while also developing your specific job skills.  You might also get opportunities to shift across job categories across your career – may be from design to testing to marketing and customer support.

Service Companies:

These companies  provide service to other companies (mostly product companies) to enable their design and development. They don’t really work on end to end product design and development life cycles nor do target any specific markets.  These are also known as companies that get outsourced parts of design and development from a client/product companies.

These companies operate mainly in two modes based on the business model:

  1. Staff Augmentation:   In this mode, the service company would help the product company (a.k.a client) to augment its short term staffing needs. A lot of times , there would be short term needs of increased resources in product companies for which they may not want to hire a full time employee (the reason being high long term costs to company).  In these scenarios, they depend on service companies to full fill short term staffing needs. The service companies charges higher bills for the employees  (based on experience and skills).  These companies makes profit on the difference between an employee’s salary and the bills that are charged from the client.
  2. Design services:  There can be two modes again in the design services business model.
    1. In one case, the company might provide certain parts of the design development as complete service. For eg: the service company might provide an entire design to implementation for a single chip design or  possibly just the design verification for a given product being developed by the client/product company.  A lot of product companies outsource some of their secondary products (products derived from a main product) development using this business model.
    2. In the second case,  a service company might design and develop generic IPs (Intellectual property)  which could be used in several SOC designs.  They  sell/licence these IPs to product companies who might be looking for accelerating their product development. In this process they also reduce costs and can focus on niche areas in the product development. Some good examples of these companies includes the ones that develop IPs and VIPs for several protocol agents like PCIE, DDR, USB, MIPI, AMBA bus agents etc.

There are a lot of service companies that starts off  by providing only staff augmentation and then might expand into one or other business models.  The staff augmentation mode is a good business model with no investment needed. All you need is to hire good engineers, place them in some other companies and bill a higher cost. Base on this model, there are also smaller service companies who provides staffing needs for a bigger service company and then together split the profit !

Design services are more difficult as the company needs good talent to design and develop IPs which is a lot similar to product companies. They would also need some good investment untill the IPs start making any revenue for the companies.  A mix of  outsourcing some secondary product development which can make some short term money while also developing IPs are also commonly seen.

An employee working in a service company would have opportunities based on how the business model and what kind of opportunities he gets.  If  he works for a client company in a staffing augmentation mode, then it depends on the client’s projects.  If he works on development of an independent IP, then he might  get more exposure to an longer design and development cycle.

The post Product Companies vs Service Companies in VLSI appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

In SystemVerilog based OVM/UVM methodologies,  UVM sequences are objects with limited life time unlike a component which has a lifetime through out simulation.

UVM Testbench – Sequences vs  Components

Refer following standard UVM test bench diagram for a general concept.  All components like  test, env, scoreboard, agent, monitor, sequencer and driver  are derived from   uvm_component  base class.  These are constructed at beginning of simulation in  a hierarchy – as parents and children.  All of the components can be accessed hierarchically from any other component by  traversing up till top  and further going down to any component.

 

On the other hand ,  UVM sequences , which are used a stimulus generators  are derived from the base class  uvm_sequence_item.  uvm_sequence_item is further derived from base uvm_object class.  These are not constructed at beginning of simulation and have no hierarchy associated.

As the test or simulation progresses, one or more UVM sequences are created and those are started on a sequencer. The sequencer-driver interface then sends one or more sequence items as stimulus to DUT.  Once the sequence completes generating all stimulus,  it will be de-referenced from memory.   This can be any time in the duration of a test.

Efficient Sequences – Need to query Testbench components

Sometimes to generate effective stimulus, a UVM sequence might want to query a testbench component like a monitor or a checker.  These are useful to generate efficient stimulus and sometimes reactively.  One example could be to monitor a DUT FIFO and keep sending sequence items untill it hits a full condition.   Since the sequence is not part of testbench hierarchy, this is not possible straightforward.   The only handle that a sequence will have access is the sequencer on which it is running currently.    Hence the sequence will need to access the monitor through the sequencer handle.

This is where the m_sequencer / p_sequencer concept is useful.

m_sequencer is a handle of type uvm_sequencer_base which is available by default in every sequence.

The real sequencer that connects to a driver is derived from the uvm_sequencer_base class. It is also parameterized to the sequence item type that is used to communicate to driver.

Hence to access the real sequencer on which sequence is running , we would need to typecast the m_sequencer to the real sequencer which is generally called p_sequencer. (I think this name was coined by some one initially to refer a physical sequencer. Alternatively, this can be named anything in your implementation)

Here is a simple example where a sequence wants to access a clock monitor component which is available with its sequencer


//A test_sequencer class derived from base UVM sequencer
//Lets say, it has a clock monitor component to access clock.
class test_sequencer_c extends uvm_sequencer;
  clock_monitor_c clk_monitor;
endclas

//Here is a test sequence that runs on the test_sequencer
//Lets say, sequence need access to sequencer to get access to clock monitor

class test_sequence_c extends uvm_sequence;

  test_sequencer_c p_sequencer;
  clock_monitor_c my_clock_monitor;

  task pre_body()
    //Typecast the m_sequencer base type to p_sequencer
    if(!$cast(p_sequencer, m_sequencer)) begin
      `uvm_fatal("Sequencer Type Mismatch:", " Worng Sequencer");
    end
    //get access to clock monitor
    my_clock_monitor = p_sequencer.clk_monitor;
  endtask

endclass

The post What is a p_sequencer and an m_sequencer in UVM? appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

This week, I got an invite to talk to a batch of final year Electronics Engineering Students who was undergoing a 4 week internship training as part of curriculum.

The students have completed 6 semesters of their graduation program and completed course work on Semiconductors, Digital Electronics, Embedded Systems, Micro Controllers, Verilog, C programming and were entering the final year of graduation.

A quick poll in beginning revealed, majority of them were looking to break into a job while a few were interested in higher studies. Some of them were specific to get a core job while few didn’t care and a lot of them were also clueless.

So I felt sharing my perspective of what are the current industry trends and opportunities that exists for electronics engineering graduate students

You can find the complete slides of this talk here – Industry trends and Career opportunities For Electronics students

The various choices that exists for a core job for electronics engineering graduates as per me falls into one of following categories

  1. Semiconductor/VLSI Industry
  2. Embedded Software Development
  3. System Design and PCB Design
  4. Electronics Equipment manufacturing Industries
  5. Research & Development
  6. Public Sector Units (PSU)
  7. Higher studies and Teaching

The Semiconductor Industry deals will design and manufacturing of Semiconductor devices. These are extensively used in Electronic devices and has seen continuous innovation and growth. Some of them that students can easily correlate are following

  1. Consumer Electronics – Smart phones , TVs , PCs, Communication devices
  2. Aerospace and military systems, Medical and Healthcare devices
  3. Computing – PCs, Cloud Computing, HPC (Super computers)
  4. AI, ML – Artificial Intelligence, Machine learning
  5. IOT (Internet of Things) – More and more devices connected to Internet
  6. Home and industry automation, wearable devices
  7. Autonomous Vehicles

VLSI was driven by Moore’s law and some can debate “Moore’s law is dead” but I feel it will “long live “ still

Technology Nodes have progressed from micro meters to nano meters. While there are some devices that still uses older process like (65 nm, 40 nm and 22nm), majority of current designs are manufactured in 16nm / 14 nm / 10 nm / 7nm and there are already research and actual work happening towards 5nm and 3nm.

While scaling is getting harder, there are also other emerging trends in chip design and I find following two getting good traction.

  1. Monolithic designs giving way to Heterogeneous chip designs
  2. 3D Stacking of transistors, Memories

We are already past billions of transistors in chips. Some recent chips like Nvidia Volta has 22 billions of transistors packed.

Complex chips that highlighted are Nvidia Volta, Intel Skylake core series, AMD Ryzen and Qualcomm Snapdragon takes 2 to 4 years or more of development that involves 500 and more people working. Those are some exciting opportunities for electronics engineering graduates. 

In terms of actual jobs and the various companies, I break down into following category

  1. Product Companies – These companies designs and develops ASICs, SOC, Microprocessors
    1. Intel, Nvidia, Qualcomm, AMD, Samsung, MediaTek, Broadcom, TI, ST
  2. Service Companies – These companies work on outsourced/In-house project development for major product companies
    1. Wipro, TCS, Tata Elxsi, Mirafra, Waferspace, Sasken, Mindtree and many more
  3. EDA (Electronic Design Automation) Companies – These companies build the tools that are essential for various chip design methodologies
    1. Synopsys, Cadence, Mentor Graphics, Aldec
  4. IP Design Companies – These companies focus on building and selling IP (Intellectual property) for others.
    1. ARM, MIPS (Processor core), Synopsys, Cadence etc (Memories, Protocol agents, connectivity)
  5. Fabrication (Fab) Companies – These are the companies that focus on the manufacturing, packaging and other aspects.
    1. TSMC, Global Foundries, Samsung

In terms of what skills are needed for a chip designer to break into VLSI/Semiconductor, I already wrote about same in another post here –  What are must know things for a chip design engineer ?

The next major opportunity for electronics engineering graduates exists in Embedded Systems Development. Following are some examples of what constitutes as embedded systems which are essentially micro controller based systems.

  1. Used in Home appliances, Medical electronics, Automotive and Industrial systems
  2. Intelligent temperature control inside an A/C, Smart TV, Digital Set Top Boxes
  3. Traffic lights, Factory controls, Portable Audio/Video devices,
  4. Medical devices – Scanners, Various Vital monitors
  5. Automotive entertainment, Self driving Vehicles
  6. IoT Devices – wearables, digital watches

For those electronics engineering graduates interested  in embedded system jobs, the skills are slightly different compared to VLSI/Chip designer.

 

Lastly since there are a lot of electronics engineering graduates coming out of college each year, there is good competition and students need to put some extra efforts to stand out from rest and increase their chance for employability 

Hope this helps.

Watch the full presentation Electronics Graduates – Industry Trends and Career Opportunities

Read more blogs VerificationExcellence – Blogs –

The post Opportunities For Electronics Engineering Graduates appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

Another year of writing on Quora completed (2017) with more than 300+ answers. That fell short slightly below my goal of averaging an answer per day. Nevertheless it has been another wonderful experience.

I am happy to have helped those in need through these answers in the last year related to VLSI, Semiconductor and related topics.

Just like last year, here is a summary of the top 30 answers across 6 categories – in terms of most updates, views, shares and responses

Read on if you have missed any of those as you step in to another year of learning and be thankful.

Verification Related

What is the difference between soft IP and hard IP in VLSI?

What are the common sources of “x” in simulations for an SOC/ASIC design?

What is the scope of machine learning in verification?

How does a C test case and SV test bench interact, and what is the exact run flow in a SOC?

Which one is more efficient and faster in order to verify your design in VLSI, simulation or emulation? Which one is good? Is emulation going to be used more in the future?

SystemVerilog /UVM Related

What is a p_sequencer and an m_sequencer in UVM?

What is static casting and dynamic casting, and how can we differentiate them?

What is the best way to model an out-of-order transaction driver in UVM?

How do we end test case in SoC and SV-UVM?

Is it good to start learning UVM through the IEEE std 1800.2-2017 reference manual?

VLSI/Computer Architecture

What is the largest semiconductor chip that has ever been built?

What is a Y chart in VLSI?

What interconnection will be used in future multi-core processor systems?

Will there be another mainstream architecture after x86 and ARM?

What is microarchitecture in VLSI design?

VLSI Career Related

What does the industry expect from VLSI verification engineers with different experience levels?

Is a VLSI job good for one’s career?

Is HDL coding a software job or a hardware job?

As a VLSI verification engineer, what are the things I should keep reading?

What are the different roles in verification in VLSI? How do they differ from each other?

Questions from Fresher/Entry Level Engineers

What are the challenges that a fresher will have to face after getting into the VLSI industry?

Is it true that VLSI digital design engineers are already in surplus in the industry?

Are jobs in the VLSI domain less relative to the number of graduates and number of post-graduates?

Is there any pressure in VLSI jobs?

Where/How can I find a mentor for a VLSI engineer?

Answers from My Experiences

How much time did you spend preparing for Intel’s interviews?

How hard is it for a test engineer (post silicon validation) to move on to VLSI field (front end or back end)?

What are the hard parts for a startup to make something to compete with the Intel x86?

What are all the contents should I added in resume as a verification engineer?

I’ve been an ASIC design engineer for the 15 years. I’d like to switch to a less stressful career with more growth outlook. What do you suggest?

Hope these helped you in some way or other.

Thank you and feel free to reach out with more questions and more learning in the new year 2018

Best wishes for a great new year 2018 !

PS: If you want to read a summary of previous year (2016) answers, you can find it here

My top answers of 2016 across VLSI, Semiconductor, Career, Interviews, Verification by Ramdas Mozhikunnath on Verification Excellence – Learn , Excel and Advance in Functional Verification

Also do follow blog on Verification Excellence – Learn , Excel and Advance in Functional Verification

The post My top answers of 2017 across VLSI, Semiconductor, Verification, Interviews and Career appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

One of the question that I hear most often from students or engineers are which are all the VLSI and Semiconductor Companies that exists in India / Bangalore and other cities to apply for a job

This is an attempt to list all the VLSI and Semiconductor companies those which I am aware.  (Note: This list may not be complete and I will keep updating as I know/hear more)

Major multinational VLSI companies with presence in India
  1. Intel
  2. Nvidia
  3. Qualcomm
  4. Broadcom
  5. Samsung
  6. Texas Instruments (TI)
  7. AMD
  8. ARM
  9. IBM
  10. Cisco
  11. Juniper Networks
  12. Analog Devices Inc
  13. Applied Micro Circuits  (Now Macom in 2018)
  14. ST Micro
  15. MediaTek
  16. Microchip
  17. On Semiconductors
  18. Altera ->  (Now Intel – 2017)
  19. Xlinix
  20. Microsemi
  21. Applied Materials
  22. Cypress Semiconductor
  23. NXP Semiconductor
  24. GE
  25. Robert Bosch
  26. Imagination Technologies
  27. Infinera
  28. Maxim Integrated Circuits
  29. Rambus

EDA companies related to VLSI – Tools as well as IP designs

  1. Cadence
  2. Mentor Graphics
  3. Synopsys
Other VLSI  Service companies
  1. Wipro (has a VLSI division)
  2. Infosys (has a VLSI division)
  3. HCL Technologies
  4. Smart Play -> Now acquired by Aricent
  5. Synapse Design
  6. WaferSpace
  7. Mirafra Technologies
  8. eInfo Chips
  9. T & VS( Test and Verification Solutions)
  10. Graphene Semiconductors Graphene
  11. Aceic Design Technologies
  12. OpenSilicon
  13. eInfoChips
  14. MindTree
  15. L&T Infotech
  16. TCS
Other Startups
  1. Home – | Soft Machines
  2. Ineda Systems
  3. Home – Aquantia Corp – Cisco backed networking startup
  4. NetSpeed Systems | Redefining SoC Design
  5. Soctronics – Hyderabad http://www.soctronics.com
  6. Signal Chip (RF related) SIGNALCHIP
  7. CircuitSutra Technologies
  8. SilabTech
  9. immensa-semiconductors
  10. SiconTech
  11. ChipSpirit
Public companies / Govt Organizations
  1. Bharat Electronics Ltd
  2. Defence Research and Development Organization
  3. ISRO – Government of India
  4. Welcome to Hindustan Aeronautics Limited
  5. C-DOT – Center for Development of Telematics
  6. BSNL
  7. Central Electronics Limited
  8. Welcome to Electronics Corporation of India Limited
  9. RailTel India
  10. Bhabha Atomic Research Centre ( BARC )

Note: If you know of anything else, do send me a note and I will add it to this list. 

Also read:  Blogs: Verification Excellence

The post VLSI / Semiconductor Companies – References appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 
Introduction

One of the big job opportunities in VLSI Design spectrum is  front end verification engineer. The demand for verification engineers has been increasingly over last decade and is also getting more and more importance.

Note: If you are new to VLSI Design life cycle, you might want to read  VLSI – Front end vs Back end – opportunities first

Front end Verification Engineer Career

There is a lot of confusion among entry level engineers on what opportunities exists for a VLSI Front end verification engineer career?  Many think it is a testing job and  consider it as second to a design job.  Having worked in this field for close to two decades,  I want to share my thoughts  on how one can build a career as a Verification Engineer and what all opportunities exist.

If you want a quick snippet of what  I am going to share, you can quickly read following slides, which is a talk that I did a year back to a group of young engineers.

One of the common question that every one has is  what will I be doing in 5 years if I start working as a verification engineer.  Will I be able to switch to a design engineering job?  Will the job be interesting?  Will I be only testing and debugging?   What all are the challenges?

Verification Engineer Career –  Facts

Based on my experience, I can tell for sure that there are lot of opportunities and a strong career path for  verification engineers. Over the last several years,  complexity of designs have increased and continues to increase.  Verifying a design  is always crucial as  any functional defect in the manufactured chip is going to cost huge money in terms of a new  tape out as well as there is the risk of losing a design win opportunity in market.   In the life cycle of a design, there are always bugs to be found in lesser time in every  project.

A good verification engineer need to have both hardware and software engineering skills. Along with strong foundation in Digital logic design , Computer architecture , Communication technologies and other domain knowledge,  he should be a good programmer too.  Most of current Verification infrastructure uses advanced software engineering concepts like  Object oriented programming, factory patterns,  continuous integration mechanisms as well as Hardware description languages like SystemVerilog and VHDL

You might want to read  – What makes a great Verification Engineer Career?  for more details.

Opportunities – Verification Engineer

Functional Verification still is is the major part of any Verification project cycle with Simulation based methodologies used primarily.

Formal Verification methodologies are selectively applied for specific aspects of a design. Functional Verification typically starts along with design development and some of the advanced constrained random test benches demands a lot of software programming skills along with hardware skills.

Performance Verification focuses on verification of performance aspects of the design

Power aware verification has gained lot of importance in last several years and the focus is to verify the low power design techniques implemented.

Clocking and CDC Verification has gained importance with multiple asynchronous clocks in the modern designs and has its own methodologies.

DFT (Design for Testing ) and DFM (Design for Manufacturing) involves specific design techniques to facilitate silicon testing and validation. Verifying these is orthogonal to functional testing and focuses on verifying the specific debug support techniques.

FPGA Prototyping and emulation is also currently gaining increased importance with larger and complex SOC designs. These helps in accelerating the functional verification and also stress testing with long stimulus patterns.

Hardware+Software Co-Verification is another approach used to have software development and testing progressing along with Hardware development and helps in more robust validation and identifying both software and hardware bugs before tape out.

For more learning checkout VLSI Online courses related to Verification

Also if you have a question, check out my Quora profile or ask a question

The post Verification Engineer Career- Opportunities and Path appeared first on .

Read Full Article
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

Ever came across this question on whether to work for a small company or a big company.  How do you decide between small company vs big company ? What will you like and what will you dislike ?

Here are some thoughts from my experience over last 18+ years of industry experience. I have worked at big global companies like Intel, IBM as well as at startups and small/mid-size companies.

I have had mix of good and bad experience at both and following is what I felt as the good/bad experience.

Note: The good/bad is purely my judgement and need not be same for all.

The good of working at big companies
  1. Social benefits: Every one from your family to friends will know about the big company brand and in the social circle , you feel good and more respected. Even getting a housing/personal loan, benefits from banks, buying properties etc becomes easier as people know the brand of the big company and are eager to engage you. I found this very useful in early career stage but of lesser importance towards later years.
  2. Networking with a lot of great people: You will find a lot of good people — intelligent, clever, helpful — at work that will help you learn a lot. Some of these people can be your mentors and can help shape your future career while some others can be good friends for life time. You will also find a lot of bad people and experiences that will teach you how you should not grow up in your career.
  3. Lot of perks/benefits which gives you a good feel : There is lot of emphasis on additional perks/benefits. This includes cafeteria options, Gym, different cultural clubs/activities, transportation, team outings, bonus and similar stuff which comes in addition to your monthly pay check.
  4. Learn art of politics: I didn’t have success at this, but at large companies, ,you do realize that in addition to technical skills you need to learn several other diplomacy and political skills for growth. If you are good at this, there will be opportunities to learn and build a long term career.
  5. Job and Career opportunities: Most big companies will have multiple business units and job roles and a lot of them also support employees interested in laterally moving across job roles/business units based on their aspirations. I found it useful in my early career to explore different job roles and settle on my aspirations later.
The bad of working at big companies
  1. Bureaucracy: This is the biggest killer and with larger company size this becomes an increasing hurdle for several people. Lot of weak middle management, lengthy processes, meetings without any objectives/outcomes, useless trainings etc are energy killers for a lot of employees who are creative and want to do things more efficiently and effectively.
  2. Limited work responsibilities: You are part of a bigger community with several hierarchy. You will only get to know about your work responsibilities or may be a couple of levels above and close groups with which you interact. Many a times you dont feel the importance of your project or the end goal and other opportunities.
  3. Changing business strategies: A lot of times big companies work on several projects based on potential business opportunities but based on market changes and other business factors, strategies and project directions can change. I have at least seen couple of project cancellations and definition changes that can be frustrating some times.
  4. Career development: Your career development will be totally dependent on how you find your aspirations, mentors and how you work towards it. You will see lot of competition even among peers and no body will be keen to help you. Personally I have seen lesser cohesion between smaller groups towards a final goal.
The good of working at small companies
  1. Opportunities for aggressive learning and growth: Being a smaller team you will find more opportunities and more responsibilities. You will be able to do different things with more freedom and demonstrate your creativity and intelligence in different ways. With lesser bureaucracy/hierarchy, it is more easier to introduce a change that can lead to more efficiency/effectiveness of a project.
  2. Bigger sense of ownership: You will find lesser hierarchy and get to work more closely with several business groups including architects, marketing, customers, senior managers. This will help you understand bigger picture and also gain a bigger sense of ownership for whatever small work you are doing.
  3. Ability to work with great people: Most smaller companies have people who are selectively hired and would be truly great people and innovators. There is less of competition among peers as smaller teams works more closer towards a goal that will either bring success/failure to the company.
  4. Benefits, Work-life balance : These days most of the startups/small companies also do provide a lot of flexible benefits like remote working, health benefits and even other perks which a big company provide. In my experience, I never felt I am missing on any benefits that was only available with a bigger company.
  5. You will learn the value of hard work, responsibility and accountability much better: Your learning, your growth, career, ability to learn — all depends on how you work hard and take responsibilities and accept accountability for failures. Unlike a bigger company your work has bigger impact and you will learn the importance of these faster and if you dont not learn, you will fail faster as well.
The bad of working at small companies
  1. Job stability: The success/failure of small companies depend on less number of factors compare to a bigger company. If you are working for a startup, then if the product/idea doesn’t succeed, then it is highly likely that company can go down while a big company would have several options. However if you are technically strong and capable, my experience is that you could always find a new job.
  2. Flexibility in terms of work schedule: Most of the times you may not be able to just work on a fixed slot like in a big company. Based on your nature, project priorities etc, there might be times where you will have to spend extra hours or adjust your timings etc.
  3. Financial stability: If you end up working for a company that is not financially sound, you will also have other financial instability issues like a delayed salary payment or perks etc. This is something better to avoid before you decide to work at this place.

These are based on my experience and every one would have their preference to work at a bigger or smaller company.

For me working at a few bigger companies in my early stage of career helped me in establishing a working relationship with great people and gathering a lot of skills, while also seeing what is not that good. Later in my current stage of mid career, I enjoy working with a small/mid-size company. I find more opportunities, responsibilities and flexibility in terms of working and learning while also having to deal lesser with bureaucracy.

For more read my other blogs here

The post Working at Small vs Big companies – The good and bad appeared first on .

Read Full Article

Read for later

Articles marked as Favorite are saved for later viewing.
close
  • Show original
  • .
  • Share
  • .
  • Favorite
  • .
  • Email
  • .
  • Add Tags 

Separate tags by commas
To access this feature, please upgrade your account.
Start your free month
Free Preview