Hi all, I am have started to learn about generators, interfaces and drivers in SV. I have a doubt regarding events. Now at line 49 of the TB below where I am waiting for the next_data event inside the generator class, you will see I have introduced a delay of 1 unit. I observed that if I don't add that delay the generator block doesn't wait for the next_data event to be triggered and just goes on to the next iteration so all the seq. are generated at the same simulation time. Can anyone please explain to me why does this happen? The design is as follows module add ( input [3:0] a,b, output r ..read more

Hello everyone, new here. Here is some background. I am trying to build an accelerator for a Convolution Neural Network over FPGA, and I have a question regarding the outputs for an FP multiplication module I need to build. Since the pixel values are normalized before computation, I am using an 8-bit fixed-point format with 1 signed bit and 7 fractional bits. I have 2 basic questions: After multiplication, I am left with a result that is twice as long but I need my value to be truncated to 8 bits. How can I scale down my result without compromising precision? Is there a flaw in my initial as ..read more

My iverilog simulation is stuck with following line. It seems I have a problem with the last operand of the ternary operator. wire [7:0] out; assign out = (i_jmp_imme) ? {4'b0000, mem[i_addr[3:0]][3:0]} : mem[i_addr[3:0]][7:0]; If I change the line to (changed the slicing from [7:0] to [7:1]) assign out = (i_jmp_imme) ? {4'b0000, mem[i_addr[3:0]][3:0]} : mem[i_addr[3:0]][7:1]; it suddenly works. I cant explain why, someone has an Idea? It works as well when I replace the last part with a constant like 8h'00. submitted by /u/Nado155 [visit reddit] [comments ..read more

I was assigned a task to implement the AES (Advanced Encryption Standard) in UART. In the project description, it was mentioned that the backend interface of UART should be AXI stream. What does this imply? submitted by /u/Double_Inspection_88 [visit reddit] [comments ..read more

hi guys. im new to verilog and ive been trying to make a T flip flop with structural logic. this is my code: module t_flip_flop_struct(T, CLK, Q, notQ); input T; input CLK; output Q; output notQ; wire D; xor xor_1(D, T, Q); d_flip_flop_struct d_flip_flop_instance(.D(D), .CLK(CLK), .Q(Q), .notQ(notQ)); endmodule however this doesnt work. this is because a t flip flop only inverts a signal, correct? the problem is that a d flip flops initial value is undefined, therefore X, which when negated just leaves X. this means this module is basically useless. https://preview.redd.it/9z6ihv2qw3yc1.pn ..read more

I'm looking for a simulation tool for verilog (either open source or one with a student license option). Specifically one that can handle SystemVerilog features like interfaces submitted by /u/dacti3d [visit reddit] [comments ..read more

Hello! I donwloaded VS Code and installed a verilog extension, also i downloaded icarus for verilog (including gtkWave), as i donwloaded icarus, called cmd and wrote 'iverilog' in it, it was fine. Everything was fine till i tried writing "iverilog -o test1_tb.vvp test1_tb.v " in powershell in VS Code, it says "iverilog : The term 'iverilog' is not recognized as the name of a cmdlet, function, script file, or operable program. Check the spelling of the name, or if a path was included, verify that the path is correct and try again." Thanks in advance submitted by /u/p1dstava [visit reddit] [co ..read more

Hi, I am learning SV and I came across rand and randc. I was told the latter doesn't repeat values until all the values are covered first. So in order to try it out, I had the following code: //////////////////////////// CODE///////////////////////////////////// class generator; randc bit [3:0] a,b; bit [3:0] y; constraint a_range {!(a inside {[4:8]}); !(b inside {[1:4]});} endclass module tb; generator g; int i; initial begin for (i=0;i<10;i++) begin g = new(); assert (g.randomize()) else begin $display("Failed at %t",$time); $finish; end $display("a:%d , b:%d ",g.a,g.b); #10; end end en ..read more

module Final_Project( input clk, // Clock signal input rst, // Reset signal input [11:0] schedule, // Register file containing feeding schedule (12-hour difference) output reg [6:0] seg_display // Output for seven-segment display ); // Define states parameter IDLE = 2'b00; parameter FEEDING = 2'b01; parameter REFILL = 2'b10; // Internal state register reg [1:0] state, next_state; // Counter to keep track of time reg [11:0] counter; // Seven-segment display patterns for each state parameter [6:0] IDLE_PATTERN = 7'b0110000; // Display "I" when idle parameter [6:0] FEEDING_PATTERN = 7'b0111000 ..read more

Hello! I'm trying to get started with verilog and i am having hard time understanding where do i even write code. I have seen some people said that they are using simple stuff as sublime text, however as a beginner I'd like to have some level of visualisation of components designed and output they provide submitted by /u/p1dstava [visit reddit] [comments ..read more