Your tones have no amplitude in software (-inf), Something is odd. Can you toggle the DDS mode for both channels to "Disable" then "One CW Tone"? -Travis ..read more

Yes, I have a snapshot of a 40 MHz tone, and a 10 MHz tone. Note, for the 10 MHz tone there is the 110 MHz tone, and still a 140 Mhz tone ..read more

Can you provide a plot or screenshot of these tones? Also a screenshot of the AD9081 panel from IIO-Scope? -Travis ..read more

Hi, just following up on this. Thanks ..read more

Hello, ISzekely Sorry for the delay in getting back to you; I was traveling. The recommendations worked well, and I confirmed that there was indeed a minor error in the SystemVerilog code. Thank you for your help and insights ..read more

Hi Andrei, Thankyou for your response, why is it necessary to use the entire design, is it not possible to use the tx_phy , tx_link, rx_phy and rx_link modules just? If i need to use the entire design and add microblaze instead of zynq, is it ok to replace the tx dma's and rx dma's because instead of microblaze doing the read and write of data i need to do it from own RTL which is 16 bit I and Q data coming from a outside chip to FPGA which i need to transmit via ADRV9001. And moreover is there a link where i can find the SDK design for using microblaze instead of zynq for this design. Best Re ..read more

Hi felipeffn , Did you manage to solve your issue or do you have some other questions? Please specify which comment was helpful so that other EngineerZone users that have this issue will have an answer that worked for you. Regards, -Istvan ..read more

No I definitely get 140 MHz, not 1040 Mhz. I double checked. T The 140 MHz is there always, by the way. Meaning, I can change the I/Q tone, and I see the tone mixed with 100 MHz, but there is a 140 MHz tone as well no matter what. When the DDS tone is at 40 MHz it overlays that 140 MHz and so I only see one tone. What is going on ..read more

Can you double check the frequency position? I would expect it to be at 1040 MHz. This is due to the fact that the NCOs (within the FPGA) boot at 40 MHz, which would then be upconverted to 1040 MHz by the CDUC. That is what I see on my stock system. -Travis ..read more

Hi Iulia, thank you for your help. I was able to load the application into petalinux and view the binary files but I am facing some issues on the EEPROM side of ZCU102 (unable to write to it). I am working on the issue, I will let you know if I am able to fix this. On the other hand, I still have a question about the 4-pin SPI mode option offered in AD9684. The manual states that 4-pin mode can be used if we constrain the SDO pin instead of leaving it out as high-impedance. andrei_g , you were mentioning it can only use 3-pin. Is there a way I can use the 4-pin SPI mode ..read more