I recently graduated from an Australian University in a mechatronics engineering/maths double bachelors. I am currently based in Sydney, but I would also be open to moving interstate (and international if I was able to be hired, but my chances of that wouldn't be great most likely), I had okay marks during my time at university but nothing amazing (Honours grade H2B for Aussies). During my time in university, I tried to find FPGA related internships as that was a course which I enjoyed. However, one role was a university research internship that ended up being less about FPGA work than was in ..read more

I got a cheap USB-Blaster clone and it seems to not be working in linux or windows. https://preview.redd.it/0nd9xapi32wc1.png?width=336&format=png&auto=webp&s=9bb82a48b56af9a2308a9543d90781fe1898b634 This is what it shows up as in windows. I think it may be a hardware problem but might be software, I don't really know much about this. https://preview.redd.it/wm9jzizz32wc1.png?width=616&format=png&auto=webp&s=41c7d0d5534cacaa075fceb33102c50d192654b8 The hardware seems to just be a STM32 and some regulator and some resistors and a crystal oscillator. Can anyone tell me i ..read more

Workshop is tomorrow, 4/23/24 at 10am ET Register on our website: https://bltinc.com/xilinx-training-courses/adaptive-socs-quick-start-workshop/ Details: This 4-hour online workshop explores the AMD Versal adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge of embedded software development and application partitioning. Also learn how to perform system migration to the Versal architecture. The emphasis of this course is on: Reviewing the architecture of ..read more

Hey folks, I'm diving into the world of VHDL after being working with Verilog, System Verilog and even UVM for almost 2 years. The transition has been... interesting, to say the least. Coming from a background where Verilog was my go-to for synthesis and simulation, VHDL feels like a whole new ball game. Sure, I get that VHDL has its loyal followers, but as a beginner, I'm struggling to see the appeal. It feels overly verbose compared to Verilog. Plus, Verilog has served me well in my previous projects both using Vivado and Icarus Verilog, so why fix what isn't broken? Before jumping to concl ..read more

Hey everyone, I'm trying to create a canny edge detection ip in vivado hls 2019 as part of a uni project, I've got the testbench and everything, but when I run C simulation, it just says that simulation successful, but there's no image output even tho I've given an input image to perform edge detection on. Can anyone tell me what might be a possible issue for output image not being displayed. Thanks. submitted by /u/cock-licker-moose [visit reddit] [comments ..read more

Is it possible to replace a 32Mx16 SDRAM with a DDR3 1GB 2x16 bit for the same use, if so what modification should be made/adapted ? submitted by /u/ExtremeLoad1409 [visit reddit] [comments ..read more

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I have run into an error whilst trying to program my tang nano 1k using the lushay labs vscode extension, I have placed the error below. This error appears to be part of openfpga loader and I can see that the documentation says that there are notes on gowin 1nz boards (which the tang nano 1k is) however I am fairly sure that that is not my issue. I have also installed the gowin ide as a few other issues suggested that might install relevant drivers however that did not help. I have used zadig to change the driver for the jtag to winusb which did get rid of another error, however that only got ..read more

What is the overall better major for learning about FPGA? How can you get experience in HFT FPGA without working in the industry or while studying at university? What is the difference between regular FPGA work and HFT FPGA work? Thank you! submitted by /u/CuriousJPLJR_ [visit reddit] [comments ..read more