Q1: What is UVM? What is the advantage of UVM? Ans: UVM (Universal Verification Methodology) is a standardized methodology for verifying the both complex & simple digital design in simple way. UVM Features: First methodology & second collection of class libraries for Automation Reusability through testbench Plug & Play of verification IPs Generic Testbench Development Vendor & Simulator Independent Smart Testbench i.e. generate legal stimulus as from pre-planned coverage plan Support CDV –Coverage Driven Verification Support CRV –Constraint Random Verification UVM standa ..read more

     1. What is callback ?    2. What is factory pattern ?    3. Explain the difference between data types logic and reg and wire    4. What is the need of clocking blocks ?    5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?    6. Explain Event regions in SV.    7. What are the types of coverages available in SV ?    8. What is OOPS?    9. What is inheritance and polymorphism?   10.What is the need of virtual interfaces ?   11. Explain about the v ..read more

  Embedded FPGAs   Embedded systems can be configured with FPGAs providing organizations with systems capable of accelerating their AI workloads at the edge, processing and analyzing data in real-time.FPGAs are desirable because of their ability to accelerate AI workloads. This is so because they can be configured and programmed to deliver performance similar to that offered by GPUs and ASICs. Since AI applications change rapidly, the reconfigurable and reprogrammable nature of FPGAs makes them the ideal solution because they are capable of evolving  ..read more

  TIMING CONSTRAINTS    Start with no timing constraints Use IDE to view the clock networks Create basic clocks Review Timing reports for coverage Open synthesized design .See schematic Report clock networks.Click constraints See unconstrained -------------------------------------------------------------------------------------------------------------  Before editing go for report_clocks Edit timing constraints   Click generated clock Description: Create a generated clock object   Syntax: create_generated_clock  [-name <arg>] [-source <args>] [-e ..read more

  Clone an existing repository $ git clone ssh://user@domain.com/repo.git  Create a new local repository $ git init    LOCAL CHANGES  Changed files in your working directory $ git status  Changes to tracked files $ git diff  Add all current changes to the next commit $ git add .  Add some changes in <file> to the next commit $ git add -p <file>  Commit all local changes in tracked files $ git commit -a  Commit previously staged changes $ git commit  Change the last commit  Don奏 amend published commits! $ git commit --amend ..read more

  STA 1.From rtl  through Verdi how can we get the constraint info.   If we want to work with 5 Mhz lets go with 6mhz By soucing Verdi we can get it from the waveform the constraint info. Specs we  know clock and reset only. 2. Will we do the STA flow as below. set search_path set link_path read_db read_verilog link_design 3. Then we do the constraints like create_clock and if needed create_generated clock Provided inputs from the  designer 4.   set_clock_transition   set_clock_uncertainty( basis-oscillator spec,pll,vco)    set_clock_latency 5 ..read more

  RTL DEBUG RTL debugging is nothing but finding the bugs in the RTL design and fix it.The bugs might arise because of multiple reasons like incorrect syntax which gives rise to syntax errors and most of the time the compiler is smart enough to notify about these errors. Other set of errors are functional and logical errors which might arise because of:- Inference of latches in the RTL design because of incomplete case/if..else statement which gives rise to race condition which in turn gives rise to erroneous results. Not proper usage of Verilog full case and parallel case and not usi ..read more

            Equivalence Checking RTL vs RTL) would be the use of equivalence checkers which were traditionally oriented towards combinational equivalence checking but have some sequential capabilities. The advantage is that these tools are well known to designers and are fairly mature. However, the tools are still primarily oriented towards verifying the output of a synthesis tool. These tools are able to deal with some changes in state encoding, allowing a synthesis tool to perform some retiming operations. However, the debug environment is not ideally suite ..read more

 Engineering Change Order (ECO) is the process of making local changes to the design netlist without re-running the entire synthesis and P&R from scratch. • ECO Types:  • Functional ECO • Change the functionality of the design • Non-functional ECO: • Fix timing, cross talk • Stage: • Pre-masks • Usage of standard cells to implement the modifications • Post-masks • Base layer taped-out, metal fix using spare cells As with other types of formal analysis, equivalence checking of a large design is a tough mathematical problem. For most ASICs and simple FPGAs, the problem can be simpl ..read more

  Define the architecture functions  Define subsystem logic components to support arch functions  Provide interfaces between logic components of sub system  Do packaging of subsystem to provide Integrated SoC  Validate SoC with integrated sub system Define subsystem components Instances Subsystem connectivity  Inputs Design files  Intent command files  Interactively entered design intent  Tech files with documentation files  Verification files  Interface definition  Optional files  Package information Load the design Design confi ..read more