Not sure, if it’s correct sub to ask this question but here goes nothing! Im computer graduate and have been working as software developer but, I have always been fascinated by electronics, I really want to switch to design engineering or verification engineering (as fresher than maybe move to design). Through some research, it seems verilog is primary requirement for the most companies. So, how well I can learn verilog to get in this field as a fresher? Also, does this industry even allow freshers? submitted by /u/prophet-of-solitude [visit reddit] [comments ..read more

All I have found is some very old documents from various Universities from the early 2000's and the IEEE 1400 page Verilog document. I am currently writing logic gates in the nand2tetris HDL and I wanted to write them in Verilog as well but I cannot find anywhere to just learn how to write a simple design. submitted by /u/Think_Apricot6134 [visit reddit] [comments ..read more

// testbench import cocotb from cocotb.triggers import Timer, RisingEdge from cocotb.clock import Clock async def reset_seq(dut): dut.RST_N.value = 1 await Timer(1, "ns") dut.RST_N.value = 0 await Timer(1, "ns") await RisingEdge(dut.CLK) dut.RST_N.value = 1 pass @cocotb.test() async def test_case(dut): dut.EN_next.value = 0 dut.EN_start.value = 0 cocotb.start_soon(Clock(dut.CLK, 10, units="ns").start()) cocotb.start_soon(reset_seq(dut)) values = range(5) results = [] await Timer(10, "ns") await RisingEdge(dut.CLK) dut.EN_start.value = 1 await RisingEdge(dut.CLK) dut.EN_start.value = 0 for id ..read more

Hi! I would like to use $clog2 in the declaration of an input bus: input logic [$clog2(WIDTH)-1:0] sig However, when WIDTH=1 the $clog2(WIDTH) equals 0 and the resulting range is [-1:0]. I guess the following can be done to resolve this issue: input logic [$clog2(WIDTH)-1+(WIDTH==1):0] sig Is there a more elegant way? Is there a problem with the above solution? Thanks! submitted by /u/The_Shlopkin [visit reddit] [comments ..read more

submitted by /u/Baba_Yaga4543 [visit reddit] [comments ..read more

Hi all! I've been assigned to make a RO-PUF circuit. Right now I'm writing down the program for the same but even after going through Github and ChatGPT/Gemini. I don't really have an experience working with Verilog so any help would be appreciated. The errors that I'm getting while trying to run this design are of this type: design.sv:113: warning: Port 1 (enable) of ring_osc_series expects 32 bits, got 1. design.sv:113: : Padding 31 high bits of the port. design.sv:66: error: reg output_data; cannot be driven by primitives or continuous assignment. design.sv:66: error: Output port expres ..read more

How to synthesis a verilog .v file uding yosys from command prompt I tried adding yosys to environment variables but it is not working Actually my project is to invoke yosys from a python script submitted by /u/Abhishek_315 [visit reddit] [comments ..read more

Hi all, I am looking to define a 3D array in my project and I am coming unstuck when finding information online, so I thought I would ask for help here. Say if I were to declare an array as such: module my_module( parameter WIDTH=64, parameter DEPTH=4, parameter INDEX=4, )( input reg[WIDTH-1:0] my_array[INDEX-1:0][DEPTH-1:0] ); Is this treated as a Index number of 2D arrays, each size WIDTHxDEPTH? If so, can I then operate on columns and rows with normal operations? I think I am essentially asking whether this is a packed or an unpacked array. Kind regards. submitted by /u/Altruistic_Score55 ..read more

I have two implementations of the adder module: one named parallel_adder and another named FA. When I use the parallel_adder implementation in my multiplier and divider, I get correct results. However, when I switch to using the CSelA32 implementation of the adder in the same multiplier and divider modules, I start getting incorrect results. Specifically, when I use 33-bit numbers(the 33th bit is for sign for operation in multiplier and divider), (e.g., 32'd4 and 32'd2), the CSelA32 implementation generates incorrect results, while the parallel_adder implementation produces the correct output ..read more

submitted by /u/Air_Hawk_2661 [visit reddit] [comments ..read more