Forum Post: RE: "ILA clock has stopped" error when trying to arm debug hab clocked by AD9361 l_clk
Analog Devices, Inc. - FPGA Reference Designs
by Matt139
3h ago
Hello, as far as I can remember, the problem has been solved by improving the amplitude of the clock signal. We just replaced some resistors or capacitors with new ones, having different parameters. But, please note that we used own-designed PCB. So, there might have appeared some phenomena which are rather not expected when you use standard boards. Also, please note that we modified the original reference design - our IP core is clocked by original l_clk, not the one divided by 2 or 4 ..read more
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Forum Post: RE: AXI-AD9361 internal delays
Analog Devices, Inc. - FPGA Reference Designs
by iulia
3h ago
Hi Dan, To move things forward a little bit, [quote userid="43593" url="~/fpga/f/q-a/579735/axi-ad9361-internal-delays/521146"]Have you calculated the digital delay based on the userguide to make sure its possible to meet your requirement?[/quote] did you get to calculate what my colleague has asked you? Best regards, Iulia ..read more
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Forum Post: RE: "ILA clock has stopped" error when trying to arm debug hab clocked by AD9361 l_clk
Analog Devices, Inc. - FPGA Reference Designs
by aperZ
6h ago
Dear Matt, Apologies for the necroposting, but I've seen multiple of your posts, and we are trying to do the same thing. I am also trying to debug a QPSK transceiver on an ADRV9364-Z7020, and can't arm the ILA with the l_clk to debug some issues I'm having with the dac_valid_* signals, and when I'm providing the data through the rfifo. I've seen that you managed to use the ILA to debug this clock domain, but I'm not sure how to do it on my side. Could you provide any hints ..read more
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Forum Post: RE: Board preset for EVAL-TPG-ZYNQ3
Analog Devices, Inc. - FPGA Reference Designs
by iulia
9h ago
Hi, [quote userid="34872" url="~/fpga/f/q-a/581621/board-preset-for-eval-tpg-zynq3"]Can i rebuild the project by changing the part to "-3 speed grade""[/quote] This should do the trick. You should add them in your project with AD9680 just like it was added in this DAQ3 project: https://github.com/analogdevicesinc/hdl/blob/main/projects/daq3/zc706/system_project.tcl#L43-L44 Best regards, Iulia ..read more
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Forum Post: EVAL-AD9081 reference design for ADS10-V1EBZ
Analog Devices, Inc. - FPGA Reference Designs
by rdb9879
18h ago
Hello, is there a FPGA reference design available for the ADS10-V1EBZ targeting the EVAL-AD9081? Can't seem to find it ..read more
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Forum Post: GNU RADIO: FMCOMMS5 on ZC702: Channel not enabled OR Unable to create buffer!
Analog Devices, Inc. - FPGA Reference Designs
by JPdev
21h ago
Currently I am trying to get all channels on the FMCOMMS5 Board on ZC702 working. I have the image_2023-12-13-ADI-Kuiper-full image running on the board with the only change is installing IIOD. I am running the latest GNU Radio Companion 3.10.9.2 (Python 3.11.7) on my Windows 10 machine. And communicating over ethernet. Using the IIO Device Sink with device: cf-ad9361-dds-core-lpc device_phy: ad9361-phy channels: '["voltage0","voltage1"]' And the IIO DEVICE Source: device: cf-ad9361-A device_phy: ad9361-phy channels: '["voltage0","voltage1"]' work as expected. The problem is I get errors when ..read more
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Forum Post: RE: Unexpected Output Tones in AD9082 ZC706 Reference Design Port
Analog Devices, Inc. - FPGA Reference Designs
by iulia
1d ago
Hi, fpga_refclk_in pins: you can leave them as they are, and if you receive SYSREF alignment error, then you should program HMC7044 to add some delays (this can be done through no-OS but I can't point to it exactly now) clkin10 and clkin0: that should be fine fpga_serdin: take a look at this commit ; here my colleague is setting TX_LANE_INVERT to 5, so to invert line 5, and then he's changing the lane mapping using ad_xcvrcon procedure. Here you have an explanation of the list of lanes, the remapping scheme: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms11-ebz/reference_hdl#data ..read more
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Forum Post: RE: Unable to communicate using SPI while connecting AD9684 with ZCU102 via FMC-HPC
Analog Devices, Inc. - FPGA Reference Designs
by iulia
1d ago
[quote userid="116035" url="~/fpga/f/q-a/580693/unable-to-communicate-using-spi-while-connecting-ad9684-with-zcu102-via-fmc-hpc/524483"]I am actually referring to the fru_dump utility[/quote] Oh, sorry, I understood that you wanted SCUI installed. It is not necessary to use the -t (tuning) option. You can just use fru-dump -i /path/to/bin/file -o /sys/path/to/your/eeprom and that's it (you need to have the .bin file copied locally). I suggest you to use our Kuiper Linux SD card image, because you write this once and it remains. The -t parameter sets tuning parameters and it expects a string (s ..read more
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Forum Post: RE: About the Channel CPACK Utility Core IP output data in the ADRV9009 ZC706 reference design
Analog Devices, Inc. - FPGA Reference Designs
by iulia
1d ago
Hi, We are currently investigating this and will get back to you as soon as we have an answer. Thank you for your patience, Iulia ..read more
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Forum Post: RE: Running reference design using AD9081-FMCA-EBZ + ZCU102(REV 1.1), IRQB0 is red, no output on iio_scope
Analog Devices, Inc. - FPGA Reference Designs
by iulia
1d ago
Hi, The IRQB0 led should not impact your ability to run the system properly. I have tried our latest release files and for me it works without an issue, even if the led is turning on red as you mentioned. Have you tried with the files from one of our releases? Can you give me the output of the "dmesg" command in the terminal connected to your board? And also for "jesd_status". Best regards, Iulia ..read more
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