Implementing randc behavior using regular constraints in SystemVerilog
Verification Excellence
by Ramdas
4y ago
In SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range.  For eg: consider  a 2 bit variable declared as     randc bit [1:0] y; Every time this variable is randomized,  the values are iterated over the possible range (in this case 0,1,2,3)  and no value will be repeated until the range is completely iterated.  One common questions asked in interviews is to implement this behavior without using randc variables. Here is one implementation that I can think off .  The example shows a ..read more
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What is a Verification Test plan ?
Verification Excellence
by Ramdas
4y ago
What is a Verification Test plan? What are details to be included in a Test plan? Why is it important in functional Verification? What are some sample test plan templates? How is a Verification Test plan used and helpful? Design Specification A design specification (also known Architecture/ Micro architecture Specification) is a document that is developed by an architect or micro-architect capturing all the details of a design and its implementation. This would include all the supported features, interfaces and protocols , configuration and initialization information including regi ..read more
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How similar is an ASIC verification job compared to a Software coding profile?
Verification Excellence
by Ramdas
4y ago
An ASIC or SOC Verification job is increasingly becoming like a Software coding and debugging profile. However what is different is that you also need to be thinking like a hardware engineer while you apply some of the software engineering practices in coding and debug. Most of Verification infrastructure (test bench, stimulus generation, build, regression, triage) all needs coding. Most of current complex designs are functionally verified using simulation and the test bench infrastructure is coded usingobject oriented programming concepts. SystemVerilog language and the UVM base clas ..read more
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Product Companies vs Service Companies in VLSI
Verification Excellence
by Ramdas
4y ago
There are mainly two types of companies in the VLSI/Semiconductor industry. Quite often entry level engineers gets confused between these and wonder what are the differences and which one is better in terms of career.    Here are some details which hopefully will give you some insights. Product Companies : The companies designs and develops products for one or more applications focusing one or more markets. The product could be a single chip (ASIC/SOC) or a platform solution with multiple chips and associated software. These companies work on end to end design life cycle.  i.e  starting from i ..read more
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VLSI / Semiconductor Companies – References
Verification Excellence
by Ramdas
4y ago
One of the question that I hear most often from students or engineers are which are all the VLSI and Semiconductor Companies that exists in India / Bangalore and other cities to apply for a job This is an attempt to list all the VLSI and Semiconductor companies those which I am aware.  (Note: This list may not be complete and I will keep updating as I know/hear more) Major multinational VLSI companies with presence in India Intel Nvidia Qualcomm Broadcom Samsung Texas Instruments (TI) AMD ARM IBM Cisco Juniper Networks Analog Devices Inc Applied Micro Circuits  (Now Macom in 2018) ST Micro Med ..read more
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Verification Engineer Career- Opportunities and Path
Verification Excellence
by Ramdas
4y ago
Introduction One of the big job opportunities in VLSI Design spectrum is  front end verification engineer. The demand for verification engineers has been increasingly over last decade and is also getting more and more importance. Note: If you are new to VLSI Design life cycle, you might want to read  VLSI – Front end vs Back end – opportunities first Front end Verification Engineer Career There is a lot of confusion among entry level engineers on what opportunities exists for a VLSI Front end verification engineer career?  Many think it is a testing job and  consider it as second to a design j ..read more
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Working at Small vs Big companies – The good and bad
Verification Excellence
by Ramdas
4y ago
Ever came across this question on whether to work for a small company or a big company.  How do you decide between small company vs big company ? What will you like and what will you dislike ? Here are some thoughts from my experience over last 18+ years of industry experience. I have worked at big global companies like Intel, IBM as well as at startups and small/mid-size companies. I have had mix of good and bad experience at both and following is what I felt as the good/bad experience. Note: The good/bad is purely my judgement and need not be same for all. The good of working at big companie ..read more
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VLSI Design – Front End and Back End
Verification Excellence
by Ramdas
4y ago
In VLSI design, what is VLSI Front  end  and what is VLSI Back end ?  What does a front end engineer do compared to a back end engineer in the vlsi design flow ?  Who has better opportunities in terms of career and earning potential?  These are some common questions that every  student or an entry level engineer encounters. Introduction: Lets try to  understand this in detail.  Following diagram illustrates a standard VLSI Design life cycle and the various stages involved in a design from specification to manufacturing. Specification: This is the first stage in the design process where we d ..read more
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What is a p_sequencer and an m_sequencer in UVM?
Verification Excellence
by Ramdas
4y ago
In SystemVerilog based OVM/UVM methodologies,  UVM sequences are objects with limited life time unlike a component which has a lifetime through out simulation. UVM Testbench – Sequences vs  Components Refer following standard UVM test bench diagram for a general concept.  All components like  test, env, scoreboard, agent, monitor, sequencer and driver  are derived from   uvm_component  base class.  These are constructed at beginning of simulation in  a hierarchy – as parents and children.  All of the components can be accessed hierarchically from any other component by  traversing up till top ..read more
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What are must know things for a chip design engineer ?
Verification Excellence
by Ramdas
4y ago
Chip design engineer skills are learned through experience over years.  It  is hard to give a comprehensive single list that is needed nor is it possible to learn everything before you start working as a chip design engineer. Having said that, following are  some of the must-know things as you start your journey through a chip designer career. Fundamentals of digital logic design. These are must to make you think as a chip designer, be able to microarchitect the design in terms of logic blocks, interconnects and synthesizing into right constructs etc. Fundamentals of analog circuit design ..read more
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