FPGA Related Forums
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Welcome to FPGA Related Forums, a portal for FPGA engineers, with blogs, forums, free documents, and a complete vendors directory soon to be published. Discuss everything programmable logic related, learn to implement a folded FIR on FPGA, talk about circuits, and more.
FPGA Related Forums
2M ago
Hello,Currently im evaluating the usefulness of frequency domain filtering in FPGA for one of our projects. Im stuck with a problem that my limited knowledge of ..read more
FPGA Related Forums
3M ago
I own a Pynq Z1 FPGA board without built-in Wi-Fi. How can I connect a Wi-Fi module, specifically using GPIO or communication interfaces like UART, SPI, or I2C ..read more
FPGA Related Forums
5M ago
Hi all,My design uses Xilinx's FFT LogiCORE IP which I use to do FFT of transform length 128 points. I configure the IP core in Vivado GUI, instantiate in my code ..read more
FPGA Related Forums
7M ago
Hi! My name is Mason. I've recently been messing around with FPGAs, and I think I found a way to do N-body simulation in O(n) time. First, some quick background ..read more
FPGA Related Forums
1y ago
Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on ..read more
FPGA Related Forums
1y ago
I have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior. I'm pretty sure it's due to timing constraint issues ..read more
FPGA Related Forums
1y ago
Hi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html).I ..read more
FPGA Related Forums
1y ago
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal ..read more
FPGA Related Forums
1y ago
HiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the ..read more
FPGA Related Forums
1y ago
Hello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples ..read more