Thanks for the reply! I can now successfully divide two signals and view the output on the oscilloscope though I feel like I have to do some calibration. I would like to now connect the output of this division process as the input to the PID controller. I can see PID_11, PID_12, PID_21 and PID_22. I see that the outputs of PID_11 and PID_12 are summed up as are the other two. Could you please mention where I could include now this division process? Until now I wrote a new module replacing the PID controller. Now I would like to copy the code from the new module and paste it in the PID one whe ..read more

Thanks! that seems like the best idea. Best method for decimation? Could it be tunnable? Like, when working with a 100 Hz signal, acquire 1 of every 100 and when working when 1000 Hz, acquire 1 of every 100 and so on? I would also love any insight into how to send a trigger (maybe from PS?) to start the data acquisition. Is that doable, maybe from python? I would like to send that trigger, acquire, and then save the data when t_last arrive. Any implementation doing a similar thing would be very welcome. Thanks in advance. Statistics: Posted by javiruni10 — Thu May 02, 2024 11:59 am ..read more

redpitaya, I completely understand, thank you so much for the detailed answers! Statistics: Posted by sslerose — Tue Apr 30, 2024 4:14 pm ..read more

Update, I tried running a continuous generation script in Jupyter and found that I could operate the oscilloscope application alongside it. I was disconnected from my STEMlab 125-14 a few times while I was doing this and I had to re-run my Python code, but it more or less worked out. I also realized that I can simply use the signal generator app within the oscilloscope app, so Jupyer is not necessary and I have answered my own question. However, I found that when I used the arbitrary signal generation in Jupyter to generate an exponentially decaying pulse that I pass to OUT1, my baseline ho ..read more

Hello again, Thank you for the information! My plan at this point is to pass ADC1 data from the PS to my module and then to channel 1 of the oscilloscope module while routing ADC2 data directly to channel 2 of the oscilloscope. I do have a small follow-up question: can I run both JuptyerLab and the oscilloscope application simultaneously? I would like to use the Python API to generate a test signal and then use the oscilloscope app to interactively view the outputs. Thank you in advance! Statistics: Posted by sslerose — Fri Apr 26, 2024 6:10 pm ..read more

Thanks a ton for your reply! I use OS 1.04 version and while there I could get PID running with PyRPL (after making some changes in the code). I would just like to divide signals and send it to the PID module. First Question: I have attempted replacing the PID module with a custom 'adder'' that uses the same register space (please see below) and adds input 1 and input 2. I would like to now try division but the modification from '+' to '/' does not work: Code: division: process(dat_a_i,dat_b_i) begin dat_a_o <= dat_a_i / dat_b_i ; end process; How can I do the division? I g ..read more

Hello fpgaSim123, I am moving this to FPGA-related topics. Yeah, that sounds doable with PyRPL as you have access to both inputs and pid modules: https://pyrpl.readthedocs.io/en/latest/ ... api-manual. You will have to use OS 1.04-28 or older to work with PyRPL. You can also check if Linien is useful to you - it does have a PID-only mode (works on 2.00 OS), but it is meant more as a standalone application: https://github.com/linien-org/linien Since the PyRPL is most likely not going to be maintained by the authors, we are planning to include it in our official OS and fully support it in th ..read more

Hello, I am new to programing FPGA I would like to use the PID module for locking but I see that it accepts only one input. I would like to divide two signals (from in1 and in2), send the quotient as the input to the PID module where I choose a set point and attempt at lock the phase of an interferometer. Is this doable using PyRPL itself or would I have to build an FPGA image? If so, could someone assist me in modifying the existing FPGA code? As in where I need to write the division stuff and connect the quotient to the PID module? Thanks in advance Statistics: Posted by fpgaSim123 — We ..read more

We are exploring the options for exporting the ADC clock from one Red Pitaya to the Ext. clck. +/- input pins of another Red Pitaya, that is pins 23-24 on E2 connector. There's an old forum thread that touched upon this question - viewtopic.php?t=1012 One suggestion there is to drive clock-capable pair of pins, e.g. DIO3 P and N with the 125 MHz clock signal, but it does not mention the proper constraints. There's a couple of clock output examples in the official github, e.g adc_clk_o is configured with LVCMOS18 single-ended standard and is driven with a pair of ODDR primitives. On the othe ..read more

Yeah, we had some acquisition glitch issues in the Oscilloscope application for channels 3 and 4 on the 4-Input. They are fixed in the 2.00-35 Beta version of the OS (the glitches are only in the application and should not affect the other measurements). Thank you for reporting this. Statistics: Posted by redpitaya — Tue Apr 23, 2024 2:05 pm ..read more