Hi,  Thanks for your response i will check that.   i want to confirm that sgdma support is there or not.  why bsp is generating mSGDMA library files in firmware even FPGA qsys design contains sgdma ip (sopcinfo).  We faced this issue. after that only we moved to msgdma ip use.  Whether we are moving in right direction. Please confirm this ..read more

Hello, Thank you for submitting your question in Intel Community. I'm Adzim, application engineer will assist you in this case. The Row address width of 12 is no longer available in current Quartus edition due to the memory longevity. Please select a value suitable for your memory component that available in the IP parameter editor. Regards, Adzim ..read more

Hi, Create a new vwf and save that vwf to the default location. Does the problem still persist? Thanks, Regards, Sheng ..read more

Hello,   As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.   Best regards, Nazrul Naim ..read more

Hello   Actually this 0-ohm resistor is do connected on the board even according to the flash datasheet it can be left unconnected. Thank you.   Alex ..read more

I'll try to generate minimal test case ..read more

Hi   I found the issue,   My design includes two clock gates in a row. When I remove the second clock gate, Quartus successfully convert the first clock gate. Why does this happen? Is there any option to resolve it?   Bu the way, the message from Quartus is unclear in understanding the issue:   Reason not converted : Found unsupported gate top|cnvr|cnvr_tlgc_inst|cnvr_scu_ins|cnvr_scu_seq_ins|block_gated_clk_seq_ins|stdc__clk_enable_nlt_reg|gcw__ckltchand|CPEN in the gated clock tree     ..read more

I have seen the overview but that won't tell me if all options are available to buy. I can see that in Industrial and Automotive temperature grade only speed 5 is valid (not speed 4). I can see from the market that M64I5N, M68I5N (RoHS SnAgCU solder balls) are available. But what about without the N Suffix (SnPb solder balls)? The same with the EQFP package: E64I5N is widely available with Matte Tin (Sn) finish but what about without the N Suffix (SnPb solder)? Do you have DofC and Material Declarations for non-N suffix parts? MBGA: 5M40ZM64I5, 5M80ZM64I5, 5M80ZM68I5 ..read more

Hi, Thanks for your answers.  I wish, there was a BSP support for Agilex-7 SoC just like Arria 10 and Stratix 10 such that I wouldn't need to work at the register level if I want to work baremetal with it. If this is all about the topic, you can make it closed for now.    Regards, Balerion ..read more

Hello,   I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.   If this does address your question, please take a moment to close this service request from your mySupport account and fill ou ..read more