Hey, I was wondering if I could get some help on the following issue. I am getting latches for the registers shown in the picture and I can't figurer out why that is the case. It is a uart_rx module with an FSM. When determining the next state logic it is telling me that I am receiving inferring latches. Could I get some help on what the issue could be? (line 76-78 is inside of the SIDLE state by the way) Thanks in advance! Error Message: module code: Code: `timescale... Read more ..read more

Hi, I am coding in Verilog for a Laplacian filter where I am using a kernel as the follow is it correct to insert it like that? Code: // Define the Laplacian filter kernel reg [31:0] kernel [0:2][0:2]; initial begin kernel[0][0] = 0; kernel[0][1] = 1; kernel[0][2] = 0; kernel[1][0] = 1; kernel[1][1] = -4; kernel[1][2] = 1; kernel[2][0] = 0; kernel[2][1] = 1; kernel[2][2] = 0; end ..read more

Hi, I am familiar with using dual port Block RAMs in Xilinx FPGAs. We usually generate the Block RAM IP Core in Xilinx Vivado and configure their ports, size and memory width etc. Then we instantiate the digital design to perform read/write operations between the digital design and the Block RAMs. How do we work with DSP slices ? and do we also need to intentionally add in our design ? Do we also configure each DSP slice we need to add in our design and in what application we need to use... Read more ..read more

Hi , i have project and i use xilinx vivado 2012 but i have problem the path of fpga chip is not supported by this version , i don't know what to do and i haven't found a solution ? can someone help me ..read more

I've made an SDRAM controller unit in Verilog for Altera DE2-115 but it seems that the byte enable signals DRAM_DQM[3:0] do not actually do anything, at least on my board. Regardless whether they're set high or low, the writes and reads result in a 32 bit write or read even though they are connected to the pins defined in the DE2-115 manual. Has anyone gotten the byte enables to work with the SDRAM in DE2-115 ..read more

Hi experts and all Sifus, I have an issue here. I've used Quartus Prime Pro to create and generate EMIF ip. EMIF stands for external memory interface. I even have compiled successfully and assigned the pins following pins in the Agilex 7 development board schematics. Currently, I am supposed to use the EMIF IP generated to perform a write operation to DDR4. I can see some VHDL code generated. I don't know if that is something useful. I just don't know how to include the EMIF IP into my... Read more ..read more

Hello, I have implemented the CRC-16-CCITT (x^16 + x^12 + x^5 + 1) with Normal Polynomial 0x1021 and Initial value = x"FFFF". I have implemented the VHDL function in a package file as shown below. Code: -- CRC16 function function f_crc16_ccitt_d8 ( data_in : std_logic_vector(7 downto 0); -- Input byte data crc_in : std_logic_vector(15 downto 0)) -- Input 16 bit CRC from initial/prev stage return std_logic_vector is -- Return the final 16 bit... Read more ..read more

Hello, I am using a RAM ip in XLINUX FPGA. When I change the context of the COE file in the RAM, I found the bit file didn't change. I am wondering what's the difference between RAM and ROM with a coe files? I am guessing if I am using a ROM ip with a coe file, the bit file will be changed if I change the coe file. However, if I am using a RAM ip , the bit file will keep the same even I change the coe file. Is that right? Thanks. Kevin ..read more

I am brand new to Verilog. I am taking a course. If I am in the wrong place, please let me know. I am trying to understand how to translate the following C code into Verilog. I just do not get how. Any help is appreciated. x = 0; for (i=0; i < 3; i++ ){ x = 2x + 1; } Any explanation of how to this can be done ? I suppose this is simple code, but Verilog seems difficult ..read more

Hi I am simulating a time to digital converter using Verilog in Quartus. It consists of both coarse and fine measurement. I have already simulated counter using structural modelling. Please help me with a code to simulate a tapped delay line like in the picture. The buffers must have a delay. Please please help me ..read more