Hi, I am about to start a new big project that incorporates reading the parallel output of high speed ADC (around 100 MSPS) and sending that data over ethernet. I have some experience with microcontroller programming at a low level and I have just a tiny bit of very basic VHDL knowledge (led blink, 7 segment counter etc...) I know that this project is going to take a lot of time and effort, but I have to start it anyway... As far as I understand, for the ethernet part, I need that the FPGA... Advice is needed on FPGA dev board choice for the project ..read more

I've been exploring and learning about FPGAs with this board and its very interesting. I know the board has FLASH but I can't really make sense of how to leverage this. In Vivado I can "Program Device" after generating the bitstream but can't see how I can send the code to FLASH rather than volatile memory. I've assumed this is simple, perhaps a jumper or some setting in Vivado or in my project but it's just not... How to save the design to FLASH with an Arty A7-35T ..read more

Hello everyone! I'm currently working on a project where I have 2 seperate circuits. One with MSP430 that has an ultrasonic sensor that capture motions and the other one with an FPGA board Nexys A7 100T with a display that displays the exact time at which the motion was detected. Both circuit are communicating via Bluetooth with the help of 2 Pmod BLE modules. My question is: How can I save those clock times when the motion was detected for future purpose? I mention that I also made... FPGA Verilog Project - Saving values for future processing ..read more

hi this is my vlsi term project (stop watch) can anyone help me generating the test bench code in vhdl ..read more

Hi, I am familiar with using dual port Block RAMs in Xilinx FPGAs. We usually generate the Block RAM IP Core in Xilinx Vivado and configure their ports, size and memory width etc. Then we instantiate the digital design to perform read/write operations between the digital design and the Block RAMs. How do we work with DSP slices ? and do we also need to intentionally add in our design ? Do we also configure each DSP slice we need to add in our design and in what application we need to use... How to work with DSP slices in FPGA ..read more

Please offer an elegant solution to move one emitting LED within built-in LED bar clockwise or anticlockwise using two built-in buttons of Tang Nano ..read more

I recently completed testing a new offset heap written in C#, this is to facilitate shared memory and persistent data structures. The freelists do not use pointers but offsets, this is because the heap can be loaded into multiple processes at differing virtual addresses. But leaving all of this aside, I had to intimately understand and carefully design this in order to get solidity and it began to dawn on me that an FPGA might be able to do this, to do the arithmetic book keeping, rather... A hardware storage allocator ..read more

i rarely work with FPGAs, and even more rarely at high speeds. i need advice for selecting an FPGA to control a AD9707 DAC. this requires a clock speed of 175MHz, and has 14-bit parallel single-ended input. Has to be driven at max speed, the DAC is already almost too slow for the application. all the FPGA does is repeat a pre-defined arbitrary waveform over and over from a look-up table. Controls nothing else. waveforms will be loaded into FPGA from microcontroller. the FPGA needs to be... help selecting a suitable FPGA to control a AD9707 DAC at 175MHz ..read more

Hi to all, I wrote a code for read a 25LC1024 EEPROM (Datasheet). I use this code: EEPROM VHDL read: -- THIS IS THE VHDL CODE FOR READ 25LC1024 EEPROM. -- CLAUDIO LA ROSA LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY EEPROM25LC1024 IS... SPI EEPROM 25LC1024 VHDL question ..read more

Hi, I want to program ic "Actel a1020b" Which framwork and hardware is used to program ic Actel a1020b...plz help me ..read more