"Plugins, PCB Calculator, Planar Inductors, Digital SPICE Simulator, Via Stitching, Via Shielding, Export to PDF, Updating PCB from Netlist, etc..." are waiting for you in DipTrace 5.0 Beta. All features overview is here: DipTrace 5.0 Beta is ready for testing! Your feedback will be greatly appreciated. Download it now: https://diptrace.com/download/download-diptrace ..read more

Dear folks, I need to convert a .lyt to .grb file - how can I do it? Do you have any recommendations regarding a tool converting also .cel, .fsc, .gdt, .jpt to .grb? Thanks, Giorgia ..read more

Hello, I am having issues converting Gerbers to CAD. Tried converting Gerbers to IPC 356 or ODB++ with DipTrace and had some success, this issue is no parts or package edits are showing in valor when I upload the created CAD, it’s like I’m missing something. The ODB++ method seems to be working better a I can see the silkscreen when uploading to Valor. I wasn't getting any images when loading the IPC file. ODB & IPC I am most familiar with. I also tried converting with Pentalogic... Read more ..read more

Hello, I have a project that was made in innovus. I uploaded the .def file. In cadence allegro I would like to create a die according to the size of the PADs that are in the def file. If I follow the route specified in the manual, create an idf file, then load def, then I get 2 pictures, but I need the PADs to look like the first one If I ask a question in the wrong section, please write where I could ask it? Thanks in advance for your answer ..read more

Case I: A particular net I routed as stripline in inner layer 3 of 14 layer board with blind via.( Via imepdance is 30 ohms) Case II: Same net I routed as stripline in inner layer 12 with Pth via. ( via impedance is 37 Ohms) Please not: ** in both the cases the net is sandwiched between reference planes on adjacent layer. ** imp in inner layer is 57 ohms and ext layer is 52 ohms with a series termination of 33 ohms Can someone explain why it happened. As I was expecting blind via to give... Read more ..read more

Hello , I want to define a DRC rule for Track to polygon pour plane . In the table below there is no polygon pour. What is the name of polygon pout int he table below? Thanks ..read more

Hi, I have a general question. If a power source that can be a linear voltage regulator or a DC-DC converter is rated for a maximum current which is little more than half of the actual current needed by the components on the PCB to be designed. Can we use two identical voltage sources in the schematic and connect both voltage sources to power and ground plane ? What are the drawbacks with this solution to get the required higher current when one voltage source is not enough ..read more

Hi, How do i make the time of a "Pulse" source equal to the voltage of a node in LTspice? The attached LTspice wont work. Do you know how to solve ..read more

The below image is take from an TI reference design. You can see that they placed an ellipse and a green color symbol with 100E. I know how to put the ellipse. Can you please tell me from where I get the green color symbol with 100E ..read more

Hi guys. I'm designing a simple 2 layers PCB. I have routed the board. Now due to some issues & to make sure that PCB is updated with latest changes done in footprint library, I used the command 'Update PCB with All' and though it updated, a new issue rise up. I mean it displaced some components from their current routed locations. Any idea how to update PCB with all footprints and still avoid displacing the components from their current locations? Actually I was performing a procedure... Read more ..read more