A Computer Architect’s Guide to Designing Abstractions for Intelligent Systems
SIGARCH Blog
by Amir Yazdanbakhsh
1w ago
“The growing complexity of intelligent systems can outpace the ability of conventional computing abstractions to support them effectively.” IET REACH 2024, Amir Yazdanbakhsh. I came across this observation by Edsger Dijkstra recently while scrolling X, and it stopped me in my tracks: “The purpose of abstraction is not to be vague, but to create a ..read more
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Rising Stars in Machine Learning Systems
SIGARCH Blog
by Akanksha Atrey, Sercan Aygun, Udit Gupta, Abdulrahman Mahmoud, Lillian Pentecost, Vijay Janapa Reddi
2w ago
Introduction The increasing complexity of machine learning systems demands a new approach to their design, optimization, and deployment. While tremendous progress has been made in ML algorithms and hardware acceleration, building reliable, efficient, and scalable ML systems requires expertise that bridges traditional disciplinary boundaries. The evolution of computing offers a valuable historical parallel: just as ..read more
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Processing-in-Memory Tutorials: Experiences from Past Two Years and Thoughts Looking Forward
SIGARCH Blog
by Geraldo Oliveira, Juan Gómez-Luna, Onur Mutlu
3w ago
Processing-in-Memory (PIM) is a computing paradigm that aims to overcome the data movement bottleneck (i.e., wasted execution cycles and energy, resulting from the back-and-forth data movement between memory units and compute units) by making memory (and storage) systems compute-capable.  Explored over several decades since the 1960s, PIM systems are now becoming a reality with the ..read more
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The QuArch Experiment: Crowdsourcing a Machine Learning Dataset for Computer Architecture
SIGARCH Blog
by Shvetank Prakash and Vijay Janapa Reddi
1M ago
Introduction The rise of large language models (LLMs) and generative artificial intelligence (GenAI) presents new opportunities to build innovative tools and is already enabling revolutionary AI-based tools in various domains. However, a significant gap remains in the language model (LM) knowledge required to deliver high-quality, AI-based tools for engineers. Figure 1 illustrates the performance of ..read more
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The Undergraduate Mentoring Workshop at MICRO (uArch @ MICRO 2024)
SIGARCH Blog
by Irene Wang
1M ago
The Undergraduate Architecture Mentoring (uArch) Workshop co-located with the International Symposium on Microarchitecture (MICRO) was hosted in Austin, Texas. This year marked a significant milestone, as uArch was held twice in the same calendar year – reflecting our excitement and commitment to expanding the workshop’s reach and supporting more students.  Similar to its summer edition ..read more
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Tug of War for Secure Caches: Randomization, Partitioning, or Both?
SIGARCH Blog
by Biswabandan Panda
2M ago
This blog post is a continuation of Gururaj’s SIGARCH blog, written three years ago. It revisits the design of secure caches and, primarily, two design choices available to the designers: partitioned cache and randomized cache. In the last three years, significant advances in this field have been made resulting in multiple papers in computer architecture ..read more
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MICRO 2024 Trip Report: Success at Scale
SIGARCH Blog
by Minesh Patel
3M ago
Research-hungry, knowledge-thirsty citizens of Planet Earth swarmed Austin this November for a Texas-sized MICRO that sold out, surpassing all expectations. Hallways were packed and lines were long as General Chairs Paul Gratz, Jose Joao, and Jason Clemons showed us all that bigger is better. Just look at these record-breaking stats. Key scaling-related statistics for MICRO ..read more
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Evaluating the New ASPLOS Review Process
SIGARCH Blog
by ASPLOS Steering Committee
4M ago
TL;DR The ASPLOS Steering Committee (SC) is soliciting feedback on the new review process introduced with ASPLOS 2023. The SC welcomes input on the impact of the new process and changes being contemplated for ASPLOS 2026. Please read this whole post then complete this online survey by Nov 8, 2024. Growing Pains In 2021, the ..read more
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Hacks To Be a Great Reviewer
SIGARCH Blog
by Karu Sankaralingam
4M ago
I had an exhausting and painful experience this year with reviews for recent top-tier SIGARCH conferences – the usual ISCA, ASPLOS, HPCA, MICRO. No I am not complaining about the reviewer load. It’s reading others’ reviews of papers I was reviewing – I found the process just draining and painful. To be clear, this is ..read more
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AI in Chip Design: from Basic Tools to LLMs and AI Agents
SIGARCH Blog
by Bryan Chin, Jishen Zhao, Haoxing (Mark) Ren, Stelios Diamantidis, Hans Bouwmeester, Hanxian Huang
4M ago
New hardware capabilities have enabled transformational AI technologies in many industries and applications. One of those industries is hardware design itself, the very discipline that enabled increased AI capabilities in the first place. At Hotchips 2024, we held a tutorial to provide an overview of transformational AI technologies that are affecting how we design chips ..read more
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