As classic 2D scaling with EUV shrinks on-chip wiring, electrical resistance increases exponentially, creating power, performance and heat challenges. Moreover, as transistor counts continue to increase exponentially while 2D scaling slows, die sizes are increasing to the point where designers are hitting the “reticle limit” of chip designs. Fortunately, innovations in chip wiring will enable chipmakers to continue delivering improvements in performance and power—while advances in chip integration will give designers virtually unlimited transistor budgets. In short, “new ways to wire and integ ..read more

The industry will continue to use EUV lithography and materials engineering to push logic density scaling to the limit. In recent years, DTCO techniques have supplemented classic 2D scaling, and today, these “newer ways to shrink” contribute about half of the industry’s progress ..read more

In our Battle of Exponentials framework, data grows exponentially as Moore’s Law slows, creating increased demand for silicon and wafer fab equipment. Are there enough valuable applications to fuel data growth as capital intensity rises? We believe so. In this blog post I focus on the promise of tokenization to digitize and democratize virtually all kinds of transactions ..read more

Classic 2D Moore’s Law scaling can continue for years into the future—as long as we also solve the materials engineering and metrology channels that accompany EUV lithography ..read more

As the semiconductor industry increasingly moves from simple 2D chip designs to complex 3D designs based on multipatterning and EUV, patterning control has reached an inflection point. The optical overlay tools and techniques the semiconductor industry traditionally used to reduce errors are simply not precise enough for today’s leading-edge logic and memory chips ..read more

At the Applied Materials Master Class today, we highlight two fast-growing and highly enabling areas of the semiconductor industry. “ICAPS” silicon powers billions of new devices on the edge—including electric vehicles. No longer an afterthought, packaging now enables the benefits associated with Moore’s Law to continue even as 2D scaling slows. Today’s class demonstrates that the AI Era requires innovation across a wide range of technologies, from the edge to the cloud ..read more

To enable a more sustainable semiconductor industry, new fabs must be designed to maximize output while reducing energy consumption and emissions. In this blog post, I examine Applied Materials’ efforts to drive fab sustainability through the process equipment we develop for chipmakers. It all starts with an evolution in the mindset of how these systems are designed ..read more

The patterning challenges of today’s most advanced logic and memory chips can be solved with a new playbook that takes the industry from optical target-based approximation to actual, on-device measurements; limited statistical sampling to massive, across-wafer sampling; and single-layer patterning control to integrative multi-layer control. Applied’s new PROVision® 3E system is designed to enable this new playbook ..read more

Applied Materials recently entered a new phase of our R&D collaboration with A*STAR’s Institute of Microelectronics to accelerate materials, equipment and process technology solutions for hybrid bonding and other emerging, 3D chip integration technologies ..read more

Semiconductor growth has accelerated to higher levels that may represent a new normal as suggested by our “battle of exponentials” framework ..read more