Static timing analysis helps to find timing issues in almost all aspects of a design and is very important to have an VLSI chip with no timing problems. But there are still some cases where STA timing verification cannot be completely applied and verified. Let us discuss some of such difficulties or limitations in the below article. You can read these STA (Setup time and Hold time) and STA related problems with solutions articles to understand static timing analysis first. Calculating maximum operating frequency and checking for setup and hold time violations are described in detail. Table of ..read more

Basics of System on chip (SOC) design (IP based or Platform based) with the need of SOC, SOC architecture, Advantages of SOC, and various examples of SoCs available in the market are discussed here. A System on Chip (SOC) is nothing but an integrated circuit (IC) with full proof system or a complete computer on a single platform chip. The SOC design may be followed as an IP based design or a platform based design. Table of Contents SOC definition and its Need SOC Architecture and Components IP based SOC design SOC design flow in detail SOC Examples SOC Advantages and Disadvantages SOC des ..read more

Study material for VLSI System second semester are listed here. Important subjects like VLSI Testing and Design of ASICS will be covered in this semester. This semester becomes very crucial for the student as he has to prepare for interviews also and regular curriculum also. Also if the candidate has got less CGPA is the first semester then he has to coverup here. Along with the second semester candidate also have to revise first semester subjects like analog, digital, Verilog and basics of VLSI. Compared to second semester first semester will be bit short in time and first semester gets ove ..read more

Study material for VLSI System second semester are listed here. Important subjects like VLSI Testing and Design of ASICS will be covered in this semester. This semester becomes very crucial for the student as he has to prepare for interviews also and regular curriculum also. Also if the candidate has got less CGPA is the first semester then he has to coverup here. Along with the second semester candidate also have to revise first semester subjects like analog, digital, Verilog and basics of VLSI. Compared to second semester first semester will be bit short in time and first semester gets ov ..read more

VLSI System study material for the first semester during the M.Tech course period in NIT's and IIT's. The first semester VLSI course includes important subjects like Analog IC design, Basics of VLSI and Hardware Modelling with Verilog. Further the course also includes two labs one for Verilog HDL and one for Analog IC design. Here I will brief the importance of the subject and required study materials for each of the subjects from the courses. Also the question paper sets which will help to prepare for the exams and cycle tests. Disclaimer : We are a participant in the Amazon Services LLC ..read more

Static timing analysis (STA) based questions asked in written test of an digital interview. STA Problems to calculate setup time and hold time and maximum operating or clock frequency or minimum Time Period required. Before starting to read this article try to understand the basics of static timing analysis (STA) such as,  What is Static Timing Analysis (STA)?  Why Static Timing Analysis (STA)? Where we use STA Static Timing Analysis? What is setup time and how to avoid setup time violations. What is hold time and how to avoid hold time violations. How to calculate the maximum cloc ..read more

In the modern semiconductor industry IP (Intellectual Property) based VLSI design is trending. IP design in Semiconductor industry has become so important to enhance the production of VLSI chips. IP designs in VLSI are largely reusable in terms of logic function and design layout. IP design in VLSI with Verification capability are termed as VIPs. In this article we will try to understand the IP design life cycle in VLSI chip design. A semiconductor intellectual property (IP) core is most widely used by the VLSI Chip Design engineers in their own product designs, IP design in VLSI has various ..read more

A content-addressable memory CAM (similar to SRAM) is a associative storage memory which addresses(searches) the content present in the computer. It compares the provided input data with the table of values and returns the address of matched data location. Table of contents 1. Basics of CAM 2. CAM Cell Architecture 3. 4x4 CAM cell Array 4. Application of CAM - TLB's Basics of Content Addressable Memory(CAM) Content-addressed memory or CAM is like the combination of an SRAM with some added searching functionality to it. It does work like an SRAM such as it can read a data from the particular ..read more

Verilog always block (blocking and non-blocking assignments) is explained in detail with examples. Also generation of MUX and Decoders Verilog. In any digital interview, Verilog questions will be asked. Simple questions to confusing and tricky questions will be asked by an interviewer. He will be interested in knowing whether you are very clear with basic concepts or not. Verilog is a hardware description language makes it necessary to be learned by an digital design aspirant. Questions on blocking and non-blocking assignments, Verilog tasks vs Verilog functions, and Verilog modelling questio ..read more

In the computer architecture or computer organization(COA), cache memory is a very fast memory, which make sure the data reach from the main memory to the CPU faster. We will discuss in detail Cache hit ratio and types of cache memories in OS and The role of cache memory between CPU and main memory in computer organization and architecture.  The cache memory is nothing but a buffer between CPU and RAM. Parameters like Cache hit, Cache miss, Miss rate, Miss Penalty, Cache block, Cache line and Cache tag, we will understand all of them to increase the cache performance. We will discuss in ..read more