Press Release – for immediate release ..read more

A fireside chat about FPGA debug If you’d like to understand what Exostiv Labs focuses on, why we do this and the value we bring to the FPGA and SoC debug, verification and validation listen to the following ‘fireside chat’ style discussion. Listen to podcast now (.wav) If you think it is for you, then you can dig into details, explore our website and contact us. (The podcast was nicely generated with the help of NotebookLM). Thank you for listening. – Frederic ..read more

You can’t fix what you don’t see Whether you’re designing a single IP, an FPGA-based product, a CPU coprocessor, an ASIC, or a System on Chip (SoC), your product must work as intended—ideally flawlessly, though “good enough” often applies. The process starts with a spec, which is usually incomplete or unclear. Then comes design, where you implement the spec, followed by verification to ensure the design aligns with it. Software development runs in parallel, interacting with the hardware. Next is validation, testing the system under near-real-world conditions. Problems can arise at every stage ..read more

10 things you should know before SoC Validation 1. Validation and verification are different things 2. Emulators do not replace prototypes (and the other way round) 3. There are silicon bugs left to be found during validation 4. Design size matters 5. Each FPGA size matters 6. Speed matters 7. Number of cycles in service matter 8. Validation is a multi-faceted job 9. Not all IPs are equal 10. Tools real capabilities matter 1. Validation and verification are different things Both verification and validation are used to check the design ‘correctness’ – they however answer different questions ..read more

FPGA prototyping with massive visibility is the key to successful validation FPGA prototyping – an essential step of ASIC validation FPGA (Field-Programmable Gate Array) is a key technology for the prototyping of silicon chips and IPs. FPGA use similar silicon processes and is configured on basis of similar hardware description languages as ASIC, IP and SoC. They are used to prototype chips before the actual silicon is available together with the ability to reconfigure them indefinitely. How does Exostiv Blade impact FPGA Prototyping? There are 2 fundamental reasons to use a FPGA prototype ..read more

FPGA prototyping with massive visibility is the key to successful verification FPGA prototyping – an essential step of IP and ASIC verification FPGA (Field-Programmable Gate Array) is a key technology for the prototyping of silicon chips and IPs. FPGA use similar silicon processes and is configured on basis of similar hardware description languages as ASIC, IP and SoC. They are used to prototype chips before the actual silicon is available together with the ability to reconfigure them indefinitely. How does Exostiv Blade impact FPGA Prototyping? There are 2 fundamental reasons to use a FPGA ..read more

RTL or Netlist flow? EXOSTIV Dashboard Core Inserter and Exostiv Blade Core Inserter propose 2 alternate flows* for inserting EXOSTIV IP and Exostiv Blade IP into the target design: the ‘RTL flow’ and the ‘Netlist flow’. With the RTL flow, the IP is generated as a RTL (HDL) code ‘black box’, with a synthesized netlist underneath. EXOSTIV IP or Exostiv Blade IP are inserted ‘manually’ by the designer into the target design by editing the RTL source code (VHDL or Verilog). Once inserted, the user manually runs the synthesis and implementation (place & route) of the instrumented code. The Net ..read more

What can Exostiv Blade do for FPGA prototyping? Classifying FPGA prototyping debug and analysis methodologies. ‘FPGA Prototyping’ or ‘using FPGA boards to prototype an ASIC or a SoC’ can be done with a variety of systems. Using such a system requires additional tools to synthesize and partition the design, and importantly, to debug and analyze it. Most of these tools fall into one of the following categories: External probes: uses external instrumentation products such as scopes or protocol analyzers to run measurements from outside FPGA chips. FPGA BRAM-based logic analyzers: typically AM ..read more

Delivering High Quality Semiconductor IP with confidence Because they are the essential building blocks of modern ASIC and SoC chips, semiconductor IPs are used in a wide variety of environments, in which they are in service during extended times. Verifying that they run flawlessly in all these contexts is not an easy job: the core functionality must be verified in numerous integration contexts, at various speeds, and for interface IP, interoperability with – sometimes flawed – external equipment must be checked. Reaching these quality targets requires including FPGA prototyping in the verific ..read more

Exostiv Blade – Managing multiple sites, targets & users In this video, we demonstrate that Exostiv Blade lets you manage multiple sites, target boards and users to reach your FPGA debug, verification and test goals. In a previous demonstration, we already showed that Exostiv Blade core capabilities – that is remotely capturing trace data from inside FPGA with 25 Gbps transceiver links (click here to access the core capabilities demonstration). We have built and connected 2 separate Exostiv Blade systems – one in a 2U chassis and the other in a compact ‘tower’ chassis. Each of these syste ..read more