VLSI EDA Companies in India | Top EDA Companies
Team VLSI
by Team VLSI
1y ago
In any modern electronic chip, there are multimillion logic gates inside it. To handle the design part of any such chips engineers need to take the help of CAD tools. The CAD tools used for ASIC development is called Electronic Design and Automation (EDA) tools.  In the ecosystem of the semiconductor industry, EDA companies play a vital role. All the service/product companies take support from these EDA companies to develop any chip. The EDA companies are very specialized to solve new challenges especially related to a new technology node. Some EDA companies also work on the IP developmen ..read more
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VLSI Product Companies in India | Top 30 Semiconductor Product Companies
Team VLSI
by Team VLSI
1y ago
The electronics devices which we use on daily basis either come directly from a Semiconductor product company or the final chip developed by the product company is sold to some other company and they use the chip and make the final product and market it. Example: A Samsung mobile phone or a laptop of HP which is powered by an AMD processor. That's the reason why common people also know the name of a semiconductor product company whereas the name of a service company is not known to common people. Whereas the role of service companies is limited to supporting product/IP companies, they are the ..read more
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VLSI Service Companies in India | Top 40 VLSI Service companies
Team VLSI
by Team VLSI
1y ago
 If you are looking for a job change or you are a fresher and wanted to enter the VLSI Industry, then this article will help you a lot. It is difficult to find the company details or even a list of VLSI companies working in India. In this article, we have tried to prepare a list of all the well-known service companies working in India. We have also included the basic details of all the companies like the year of inception of the company, the City where the company has offices, the LinkedIn page link, and the website of companies. Let me explain how this article could be useful to find the ..read more
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Input Files Required for PnR and Signoff Stages
Team VLSI
by Team VLSI
1y ago
In this article, we are going to discuss the input files required in various stages of pnr and signoff. We can categories the set of inputs into two parts, one is mandatory and the other is an optional set of inputs. A. Place and Route stages:   I. Pre Placement Stage Gate level netlist  Logical Library Physical Library SDC file         Optional inputs Block partition def Pin def Power plan script Welltap placement rule Macro placement guidelines MMMC Setup file EndCap, Decap cell list Spare Cell module definition and rule Note:  (i ..read more
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TSMC 7nm, 16nm and 28nm Technology node comparisons
Team VLSI
by Team VLSI
1y ago
Before starting this article, I would like to say this topic is highly sensitive and we are not supposed to reveal any foundry data. So Instead of making comments on any data which you know and I have not given here, you may mail me along with the reference link. The purpose of writing this article is only to make aware to new people who are preparing to enter into VLSI industry in an easy way.  Kindly note that none of the data is being added from our side in this article which is not available in the public domain. You will notice that many fields I have left blank intentionally, which ..read more
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Top 20 TCL syntax helpful to improve TCL scripting skill for VLSI Engineers
Team VLSI
by Team VLSI
1y ago
One scripting language without which it will be very difficult to survive in VLSI Industry, that would definitely  be TCL (Tool Command Language). TCL is widely used everywhere in the VLSI industry because many tools are based on the tcl. We can directly interact with the tool using tcl CLI (Command Line Interpreter).  It has been observed that many beginners initially hesitate to start the TCL scripting. Most of the cases user know the basic tcl commands but how to connect all them and create a script is the only problem. I would say even you know some basic tcl commands you can sta ..read more
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Interview questions for experienced Physical Design Engineer, Question set - 9
Team VLSI
by Team VLSI
1y ago
  Code: CDN4Y072021PD Experience level: 4 Year Profile: Physical Design Engineer 1. Introduction and physical design experience 2. What major differences have you observed in the 7nm and 14nm process nodes? 3. What is the functionality of this circuit? (He drawn schematic in paint) 4. Do you think, is there any issue with the above circuit? If so what would you suggest for improvement? 5. When clock gatting circuit has added in the design RTL/Synthesis/PnR? 6. What are the checks you perform before starting the floorplan? 7. What is a library check? 8. What are the information av ..read more
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Flip-flop and Latch : Internal structures and Functions
Team VLSI
by Team VLSI
1y ago
The flip flop is the most commonly used sequential element in any ASIC design, especially the D-type flip-flop. In the D flip flop, the D indicates delay, which means the output is a delayed version of input D.  Whereas a latch is the simplest and a basic sequential element. In general, there are two latches used to make a flip flop. the flip-flop is sensitive to clock edge and the latch is sensitive to clock level. The following section will explain the internal structure and operation of flip flops and latch. In this article, we will limit our discussion to only d type flip flops and d ..read more
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Tie Cells in Physical Design
Team VLSI
by Team VLSI
1y ago
The tie cell is a standard cell, designed specially to provide the high or low signal to the input (gate terminal) of any logic gate. The high/low signal can not be applied directly to the gate of any transistors because of some limitations of transistors, especially in the lower node. The limitation will also be discussed along with the schematic and operation of tie cells in this article. We will discuss the following sub-topics in this article. Need of tie cells Schematic of tie cells The function of tie cells Placement of tie cells Need of tie cells: In the lower technology node, the g ..read more
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Integrated Clock Gating (ICG) Cell in VLSI
Team VLSI
by Team VLSI
1y ago
 Low power ASIC design is the need of the hour, especially for hand-held electronics gadgets. In all hand-held products, the customer demands more battery life. This could be possible only if our SoC (System on Chip) inside the gadget consumes lesser power. There are various low-power design techniques that are being implemented the reduce the power consumption of application-specific integrated circuits (ASIC). The clock gating technique is one of the widely used techniques for low power design. Integrated Clock Gating (ICG) Cell is a specially designed cell that is used for clock gating ..read more
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