In this next article I am going to explore a component commonly used in circuit design, specifically the FIFO buffer. A FIFO is a First-In-First-Out data structure. Our buffer design will utilize the register file created earlier. Basic Operations A FIFO is a buffer with a fixed storage capacity. And there are only two basic … Fiddling around with a FIFO circuit Read More » The post Fiddling around with a FIFO circuit appeared first on FPGA Coding ..read more

This article explores the concept of a ROM or Read-Only-Memory circuits. Today, the venerable ROM chip is rare, largely replaced by updateable non-volatile storage devices like flash memory. Before the age of flash updateable firmware, most consumer electronic devices had their data and code permanently encoded in one or more chips. If you needed to … Ruminating on the concept of ROM circuits Read More » The post Ruminating on the concept of ROM circuits appeared first on FPGA Coding ..read more

You may have heard about SystemVerilog. And if you have, maybe you have also heard that SystemVerilog is simply an extension of Verilog, focused on testing and verification. That is both partly true and partly false. Let’s explore this a bit further to learn why that is the case. A brief history of SystemVerilog As … Sussing out SystemVerilog vs. Verilog Read More » The post Sussing out SystemVerilog vs. Verilog appeared first on FPGA Coding ..read more

It is back to FPGA topics for this next article. This time we are going to be exploring register files. A register file is nothing more than an array, collection or “file” of registers. We have encountered registers before, first when I introduced sequential circuits and the Verilog reg keyword. A register is nothing more than a collection of one or more bits logically grouped together. The important part attribute of a register is that it has memory. That is, a register “remembers” and maintains the last value set until it is either changed or reset. A memory bit is typically implemented in h ..read more

I am taking a short break from FPGA topics because I want to introduce you to Firth. Firth is an experimental programming language heavily inspired by Forth. Its design goals are to be small, fast and efficient, portable and embeddable. Forth was designed by Charles Moore in 1968 to be a procedural, stack-oriented programming language and interactive environment. Forth is well-suited to running on small devices, which is why this is ultimately relevant to our interest in FPGA topics. If you are new to Forth, you can learn a lot of the basics at Easy Forth. I also highly recommend Starting For ..read more

Installing a new SSL certificate has become a periodic ritual. As I mention in my author bio I manage several websites. One or more times a year I have to repeat the process of installing new certificates on these websites. This shouldn’t be difficult, but for reasons which I’ll explain later, it is sometimes more difficult than I’d like. And each time I do this, I inevitably fail to write down the steps I take. As a result, I find that I must research and re-discover how to accomplish this task. Having once again completed this process I am going to try to break the cycle. Hopefully next time ..read more

Finite State Machines (FSM), are very important in hardware design. They represent systems that transition through a set of internal states. These transitions are defined in terms of both external inputs and the current internal state. A change to an external input causes a change to the internal state. State changes sometimes also trigger an output change. Most interesting software and hardware systems involve finite state machines in some form. Most often finite state machines act as controllers for a digital sub-system. Example uses include modules implementing communication protocols, butt ..read more

For this next project I’ll create a Pulse Width Modulation circuit. What is Pulse Width Modulation? Pulse Width Modulation (PWM), is a method of controlling average voltage or power in a digital circuit. It accomplishes this by varying the on/off duty cycle of the output signal. A duty cycle of 0 results in 0% time in the on state. It produces a constant 0V PWM output. Similarly, a duty cycle of 1 results in 100% time in the on state. It produces a constant Vmax output. And a duty cycle of, say, 60% says that the signal should be in the on state 60% of the time and off for the remaining 40% of ..read more

Previously I designed a simple configurable countdown Timer with asynchronous reset, enable and limit. Now I will add a pre-scaler to the Timer. What exactly is a pre-scaler? You can think of the pre-scaler as an integer value that scales (or divides) the timer clock signal down to a lower frequency. Why Do We Need a Pre-Scaler? Remember that the Artix-7 FPGA on the Basys 3 runs at 100Mhz. And as a result, a clock cycle lasts only 20ns. Therefore, an 8-bit countdown timer counts down from 255 to 0 in a little more than 5.1 microseconds (20ns/clock cycle * 256). With an 8-bit countdown timer we ..read more

This time I am going to create a configurable timer circuit with both an enable and a settable start value. You may recall that we’ve previously created counter circuits. For some examples see Creating a Configurable counter Circuit and Designing a Simple 4-bit Counter Circuit. Timers and counters are close related and very similar. It is perhaps easiest to think of a timer as a specialized counter for counting clock pules. Counters on the other hand can count the occurrence of any kind of event. So far I’ve used the counters primarily as timers. Unlike the counters we’ve created which counted ..read more