AMD interview Questions (Physical Design) Tell me about your experience. How will you make sure that your power structure is good? Tell me about DRC and LVS fixes. Why we are following certain guidelines for macros placement and what are those guidelines? What is the minimum space required in between macros if the channel is there on the non-pin side of macros? What is the distance between tap cells in your design? What are the setup and hold edges for a 3-level multi-cycle path? What are the setup and hold edges for the half-cycle path? How you will perform cell spreading in placement ..read more

Qualcomm Interview Question (Physical Design Engg)  1. Practical flow of the design? 2. How analog macro is placed? 3. Explain the power plan structure in your design? 4. What is the routing blockage for analog macro? 5. What are the checks after the floorplan? 6. What are the steps in the placement stage? 7. What is the block size, utilization, target skew, WNS of your design? 8. What are the corners in your design? 9. What are the corners considered in the placement stage? why? 10. What are the corners considered in the CTS stage? why? 11. What are the causes for congestion. And how to ..read more

What is the meaning of PVT corners & How these corners will affect the Delay? How OCV  (On-Chip Variation)is related to PVT? PVT: PVT is the Process, Voltage, and Temperature. In order to make our chip to work after fabrication in all the possible conditions, we simulate it at different corners of process, voltage, and temperature. These conditions are called corners. All these three parameters directly affect the delay of the cell. Process: There are millions of transistors on the single-chip as we are going to lower nodes and all the transistors in a chip cannot have the same pr ..read more

Best Positive thinking & self-motivation books Hello Friends, In today's situation, I and you all need Motivation! Because we are all doing Struggle in our life and fighting with life to create our own identity in the world! In such a pandemic situation, we are often in a deep trough of despair! So, at the time when no one helps us, only good books help us at that time and it is said that "Books are the best friend of a human being". So, friends, today I am going to share a list of some very top Motivational Books in front of you! This will change your life and you will be able to do some ..read more

What are OCV and CRPR? How they are related? CRPR (Clock Reconvergence Pessimism Removal) topic is comes after the STA introduces OCV (On Chip Variation) analysis, So here I  covered small introduction of OCV so that we can understand the CRPR and How CRPR is related to OCV. we all know during the manufacturing of chips on the same die may suffer from variations due to process, voltage, or temperature change, thus transistors can be faster or slower in different dies. Delays vary across a single die due to PVT (processor, voltage, temperature). The delay value of IC in cold weather is d ..read more

Standard Parasitic Extraction Format (SPEF) SPEF allows the representation of parasitic information of a design(R, L, and C) in an ASCII (American Standard Code for Information Interchange exchange format). A user can read and check the values in a SPEF file. Users would never create this file manually it is automatically generated by the tool. It is mainly used to pass parasitic information from one tool to another. Interconnect parasitics depends on the process. SPEF supports the specification of all the cases like best-case, typical, and worst-case values. These triplets (best, typical, a ..read more

Wire Load Model (WLM) How do you estimate the parasitics (RC) of a net before placement and routing?  Prior to the Routing stage, net parasitics and delays cannot be accurately determined we know only the fanout of net and the size of the block. Before going for floorplanning or layout, wire load models (WLM) can be used to calculate interconnect wiring delays (capacitance (C), resistance (R)), and the area overhead (A) due to interconnect. The wire load model is also used to estimate the length of a net-based upon the number of its fanouts. The wire load model depends upon the area o ..read more

Timing model in VLSI 1) Linear timing model 2) Nonlinear delay model (NLDM) Cell Delay (Gate Delay): Transistors within a gate take a finite time to switch. This means that a change in the input of a gate takes a finite time to cause a change in the output. Gate delay = f (input transition (slew) time, output load Cnet+Cpin). Cnet-->Net capacitance Cpin-->pin capacitance of the driven cell Timing model: Cell timing models are used to provide accurate timing for various instances of the cells present in the design. The timing model normally obtained from detailed circuit simulation o ..read more

Time Stealing and Time Borrowing Time borrowing: https://www.physicaldesign4u.com/2020/05/time-borrowing-concept-in-sta.html Here some more about Time borrowing ..... The High-speed CMOS clocking design style are --- time borrowing in Latches and time-stealing in Edge triggered flip flop. Since in an edge-triggered system, the operation time of each pipeline partition will never equal to others and the longest logic delay between two registers will determine the maximum clock frequency of the system. In any circuit, the concept of how to fit more combinational logic within each logic part ..read more

How the setup and hold checks are defined in the library? Can both setup and hold be negative? Sequential cells timing arcs: Sequential cells timing arcs as shown in the figure. For synchronous inputs such as D, SI, SE there are following timing arcs Setup check arc (rising and falling) Hold check arc (rising and falling) For asynchronous inputs such as CDN there are following timing arcs Recovery check arc Removal check arc Synchronous checks: setup and hold The setup and hold timing checks are needed to check the proper propagation of data through the sequential circuits. These tim ..read more