
VLSI UNIVERSE
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This blog provides insightful articles on VLSI and EDA domains ranging from frontend design to physical design. Everything you can get to know about VLSI in general and physical design in particular. Simple and easy to understand.
VLSI UNIVERSE
3w ago
In the post lockup latches, we mentioned that it may not be advisable/allowed to have a positive edge triggered flop flop followed by a negative edge-triggered flip-flops in scan chains because of DFT specific reasons. In this post, we will try to undertstand the underlying reason.
First of all, we need to understand the basics of scan timing. A usual scan cycle looks pretty much like the one below. Tester sends shift data once every one cycle, and that usually is during clock low pulse. Image1 below shows typical scanin assertion and scanout observation during shift cycles. Here, I am showin ..read more
VLSI UNIVERSE
2M ago
We frequently hear that an NMOS can pass a strong "0" and only a weak "1". Similarly, a PMOS can only pass a weak "1". But very few people actually know the reason behind this. In this post, we will delve into the details of why NMOS cannot pass a strong "1" and vice-versa.
To understand this, we have to dig deep into the behavior of MOS transistors.
Figure 1: Basic MOS structure (NMOS)
Figure 1 shows the basic structure of MOS transistor. As we know, the existence of channel (charges) is essential for it to conduct electric current. We have read that channel would exist if (Vgs > ..read more
VLSI UNIVERSE
1y ago
Logic equivalence check is normally carried out to ensure some processing of the design (example logic synthesis) has not resulted in change of functionality. It flags any logical changes with respect to a golden set of collaterals. There are many applications of logic equivalence checking, some of the prevalent ones pertaining to:
1. Logic equivalence check between RTL and corresponding synthesized netlist to ensure the logic synthesis has not introduced any functional issues
2. Logic equivalence check between two sets of netlists after doing netlist edits.
One thing to note here ..read more
VLSI UNIVERSE
2y ago
In our first post, we discussed that any programming language is a language in the first place. So it must be analogous to a language in how the constructs are used and formed in it. In this post, we will try to understand this aspect by making analogous comparison between English and C as a programming language.
As we know that any language has its character set as the most basic construct. English has Roman script as its character set, which includes a-z, A-Z. Similarly, to write a program in any programming language, you must be aware of the character set of that programming language.
The ..read more
VLSI UNIVERSE
2y ago
Before we start discussing about C as a programming language, we must be clear about the term programming language itself. Only then, we will be able to appreciate C as a programming language.
As the name suggests, programming language is a language. A language that computer understands, and that is used to interact with the heart of the computer. Obviously this language has to be understood by programmers as well, so that the interaction is understood by both the parties. In other words, through a programming language, you are giving instructions to the computer on the tasks it has to perform ..read more
VLSI UNIVERSE
2y ago
Hi there, I am a software professional with over a decade of industry experience. I am here to share my knowledge and experience with all of you, and in the process, learn a lot of things myself. As the saying goes, a good code is all that glitters. Let’s begin our journey to make our codes glitter ..read more
VLSI UNIVERSE
2y ago
In the post "setup and hold checks", we discussed the meaning and interpretation of setup and hold checks. We also discussed the terms "default setup check" and "non-default setup check" and same for hold checks. Essentially, every timing check, be it setup/hold check, data check or clock gating check follows a default edge-relationship depending upon the types of elements involved. For instance, default setup check or setup timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop is full cycle, whereas hold check path is zero cycle. Have you ever thought why ..read more
VLSI UNIVERSE
2y ago
The launch/capture event of a positive edge-triggered flip-flop happens on every positive edge of the clock, whereas that of a negative edge-triggered flip-flop occurs on the negative edge of the flip-flop. In this post, we will discuss the default setup/hold checks different cases - same clock, 1:n clock ratio clock and n:1 ratio clock. And this should cover all the possible cases of setup/hold checks.
Case 1: Both flip-flops getting same clock
Figure 1: Pos-flop to neg-flop default setup/hold checks when clocks are equal in frequency
Figure 1 shows a timing path from a positive edge-trigger ..read more
VLSI UNIVERSE
2y ago
As we know, all flip-flops which are required to be "out of reset" at the same time are placed in fanout of a single reset synchronizer. In this post, we will discuss if there is any relationship required between clock frequency of reset synchronizer and the clock frequency of the flip-flops in fanout. For now, let us assume that all the flip-flops in the fanout of reset synchronizer work on a single clock "CLK". <dsfdsf> discussed the case when the flip-flops are working on multiple clocks.
Let us first assume that reset synchronizer's clock period is N*CLK_PERIOD; i.e. reset synchron ..read more
VLSI UNIVERSE
2y ago
Design problem: A set of flip-flops, some working on 100 MHz clock and others working on 200 MHz clock are required to come out of reset together. What should be the clock of reset synchronizer
Solution: Since all the flip-flops are required to come out of reset in the same cycle, all these must get reset from a single reset synchronizer. Now, as the question states that the flip-flops in the fanout of reset synchronizer are working on two clocks. We need to find the correct-by-design clock that reset synchronizer should be working on. Let us assume that the correct clock to be connected to ..read more