Hi all , We have been in the semiconductor in for more than 8-10 years now. With the experience and expertise in the several domains we have launched courses for students/professionals to kick start their career in Semi-Space. In this post i will briefly discuss on Analog design . Analog design is a very competitive domain and in high demand.  Currently we have do not have sufficient skilled professionals to meet the demands of the industry. It is also observed that the recent graduates lack the necessary skills to be employed for a analog-design role. However , there are few recr ..read more

Adders in Vlsi are basic components for an ALU . There are N number of adders each with their own advantages & disadvantages. When two numbers are to be added and if each of them is of N bits than we can add them in Two different ways : Serial Parallel In serial addition the LSB's are added first than the carry created are propagated to the next higher bits. Whereas in parallel addition every it added in parallel without waiting for carry and different algorithms are used to compensate for the carry.             ..read more

Hello everyone. We have created a new course to help candidates crack VLSI job interviews. This course covers all the possible question that can appear in RC circuits.  RC Circuits are complex to understand. It usually takes lots of effort to get down to all the basics to solve problems on RC. Even though , there are just these two components, Yes, just Two, R and C. There can be a plethora of questions which can be asked. Watch this promo video : As this is our first course , we are offering first 100 coupons to this course. Happy learning everyone. Link : Click Here ..read more

Link for the coupons : Here Interpolation filter Design using Verilog Code. interpolation factor = 2 coefficient number =10 ={1,0,0,0,0,0,0,0,0,0} input sequence seq_in = {1,2,3,4,5,6,7,8,9....} output sequence seq_out ={1,0,2,0,3,0,4,0,5,0,6....} the below code helps us to get the interpolated sequence using interpolation factor 2 it uses the state machine and it is active low reset every 10th clock the output is generated //---------------function_multi.v------------------multiplication_function-------------------// //---------------------used the function ..read more

There are two types of state machine(FSM)they are listed as: 1:Mealy machine 2:Moore machine Mealy machine: is a FSM whose output values are determined both by its current state and the current inputs.    Moore machine: is a FSM whose output values are determined only by its current state only.         Example: 1)Mealy module: sequence detector   For the example go to the link below which is already available in our blog   httngp://verilog-code.blogspot.in/2014/08/finite-state-machine-design-for.html 2)Moore machine: traffic light contro ..read more

Link for the coupons : Here what is a state machine? It is a sequential circuit which has some predefined state. The system goes through these states as per the control signal. Transition takes place for every clock and in some cases it depends on few control signals . Applications: State machines are important part of embedded systems. Once we know that a system has to go through a set of well defined states we can design the system and make the machine to act accordingly . Here i m giving a flow which must be followed to design any state machine. 1. define the states from the sp ..read more

    FSM DESIGN MADE SIMPLE                     Hie, its been a long time since i updated my blog as i was busy with other projects. In last one month i have received many requests to provide the more details on FSM coding so here is it for you.Today i am going to explain how to create a simple FSM using verilog with an example of sequence detector. FSM is a simple system by itself and its designed to perform certain functions. Take for example traffic light controller ,lift operation, etc.           &nb ..read more

Hello everyone, Here is a tool which can be used to convert verilog to vhdl and vice-versa. I had tried a lot searching for a free tool online  and finally found this one which is cool to use and easy to operate. You can click on the link below and use it. I have tried converting few simple VHDL programs to verilog and it works fine. Here are some snapshots of one such program with steps for conversion: step 1: run the software step 2: Click on the tab  " VHDL TO VERILOG"  and also specify the destination directory where you want to save your files step 3: Click ..read more

Refer to "HDL progamming using Verilog and Vhdl " by botros for booth multiplier logic. or watch this video CODE: module booth (X, Y, Z,en);        input signed [15:0] X, Y;  input en;        output signed [31:0] Z;        reg signed [31:0] Z;        reg [1:0] temp;        integer i;        reg E1;        reg [15:0] Y1;        always @ (X, Y,en)        begin        Z = 32'd0;     ..read more