I have a fully differential op-amp. How do I measure the input referred offset of a fully differential op-amp? For comparators, I usually fix one input then ramp the other, make an expression to grab the ramp voltage at the time where the output flips. Then run that over Monte Carlo. For a single-ended op-amp, I can do it the same way I guess. By just opening the feedback loop, the high open loop gain turns it into a comparator. How do I do it for a fully differential op-amp? submitted by /u/hlm92286 [visit reddit] [comments ..read more

Of the following positions in the design flow, which have the most geographically diverse/remote work prospects, and which have the greatest number of job opportunities (USA)? Which are highest paying in the USA? Did I miss any careers in the design flow? If you had to pick as a new EE graduate, which discipline would you land in and why? RTL design Design verification Physical design DFT Post silicon verification I’m an EE student and thinking of which discipline I want to end up in. My main desire is location flexibility/remote work, as my community is based in NY which is not a hardware ..read more

Why do Innovus commands have two forms? For example floorPlan and init_design like below first form second form Is it because they come from different sources? Or is part of it a tcl command? I just started learning Innovus and don’t have a detailed understanding of these commands. If anyone can answer this for me, I would be grateful submitted by /u/CricySaray [visit reddit] [comments ..read more

​ https://preview.redd.it/761mmne0jqwc1.png?width=310&format=png&auto=webp&s=622163f8ef42a1c7c10b35b7a06a0e01d9193542 There is a requirement for a P-side current generation. Currently we have P-side Vt/R solution which is the left branch in the figure, except it is diode connected. When the PMOS is diode connected, since the current ends up being VDD dependent, I thought of an idea where gate moves with VDD. Basically when VDD increases, current through R8 increases which raises the gate of the NMOS. That causes the NMOS to pull the gate of the PMOS current mirror down (diode ..read more

Im moving into my final yeat in my undergrad in EE and am thinking of making a final year design project related to one of these domains: Accelerators (AI algorithm acceleration, DL or DNN acceleration) New IPs for RISC V (that improve upon its performance) Inmemory computing I need your help to give me pros and cons of these domains, advice on which domain has what problems in the industry and how that problem may be solved by a project (a concept). Or any other domain i might look into or any other idea for a design project. Please dont say go with the one you are most interested in or enjo ..read more

Hi everyone, I have the desire to change job. I want to explore new areas in analog design. Moreover lately workload has become impossible, working night and days and weekend too. I feel i have more responsibilities than actually I can support due to my little experience . I have sent some cvs around but none called me back. This is my cv, any suggestions? I am based in europe but I don’t want to relocate to US or germany. I am a 27M Thank you. submitted by /u/chipanalog [visit reddit] [comments ..read more

Hello. I've been trying to simulate an gate recessed AlGaN/GaN HEMT. I'm trying to model the gate leakage, however, I see that all the models are for MIS structures, wherein, I'm dealing with a gate directly recessed into the AlGaN layer. So far I've tried the tunneling contact model- but it doesn't produce a good result. Can anyone with expertise in this help me out? I'd really appreciate the help. submitted by /u/SadCrit [visit reddit] [comments ..read more

submitted by /u/SimplyExplained2022 [visit reddit] [comments ..read more

I have an interview for the role of Standard Cell Designer at major foundry, It is a fresher position. I have an experience of 2+ years working as an AE supporting Virtuoso Schematic and Layout suite along with LVS/DRC and LPE Tools. How should I go about preparing for this interview? What all would be expected of me ? Any advice/suggestions will be appreciated, Thanks. submitted by /u/eroSage112 [visit reddit] [comments ..read more

Due to financial setbacks I had to quit my M.tech course but it didn't stop me from upgrading my skills and I joined a Physical Design Professional Training and I'm looking for a job with full enthusiasm. I have currently applied to around 30 positions but still waiting on the response. Please help me figure out the cause of this setback. submitted by /u/diabolical775 [visit reddit] [comments ..read more