Memory System Benchmarking, Simulation, And Application Profiling Via A Memory Stress Framework
Semiconductor Engineering
by Technical Paper Link
14h ago
A technical paper titled “A Mess of Memory System Benchmarking, Simulation and Application Profiling” was published by researchers at Barcelona Supercomputing Center, Unversitat Politecnica de Catalunya, and Micron Technology (Italy). Abstract: “The Memory stress (Mess) framework provides a unified view of the memory system benchmarking, simulation and application profiling. The Mess benchmark provides a holistic and detailed memory system characterization. It is based on hundreds of measurements that are represented as a family of bandwidth-latency curves. The benchmark increases the coverage ..read more
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Electromigration And IR Drop At Advanced Nodes
Semiconductor Engineering
by Ed Sperling
14h ago
Manufacturing chips at 3nm and below is a challenge, but it’s only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wilson, product management director for Calibre Design Solutions at Siemens EDA, talks about what’s needed to get a design ready for manufacturing, what’s involved in a DRC-clean design, and how that can he ..read more
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Blog Review: May 22
Semiconductor Engineering
by Jesse Allen
1d ago
Cadence’s Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled. Siemens’ Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain specialists working concurrently in real-time. Synopsys’ Hezi Saar expects the integration of AI capabilities into IoT devices to drive demand for high-performance and low-latency memory interfaces on low leaka ..read more
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Compilation Challenges Of Scaling Up Quantum Computing With Superconducting Chiplet Architecture
Semiconductor Engineering
by Technical Paper Link
1d ago
A technical paper titled “MECH: Multi-Entry Communication Highway for Superconducting Quantum Chiplets” was published by researchers at University of California San Diego, University of California Santa Barbara, and Cisco Quantum Lab. Abstract: “Chiplet architecture is an emerging architecture for quantum computing that could significantly increase qubit resources with its great scalability and modularity. However, as the computing scale increases, communication between qubits would become a more severe bottleneck due to the long routing distances. In this paper, we propose a multi-entry commu ..read more
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Ferroelectric Memory-Based IMC for ML Workloads
Semiconductor Engineering
by Technical Paper Link
1d ago
A new technical paper titled “Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads” was published by researchers at Purdue University. Abstract “This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and&nb ..read more
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Proof-of-Concept On-Chip Flow Cytometer Using Integrated Photonics (imec, Sarcura)
Semiconductor Engineering
by Technical Paper Link
2d ago
A new technical paper titled “On-chip flow cytometer using integrated photonics for the detection of human leukocytes” was published by researchers at imec and Sarcura GmbH. Abstract “Differentiation between leukocyte subtypes like monocytes and lymphocytes is essential for cell therapy and research applications. To guarantee the cost-effective delivery of functional cells in cell therapies, billions of cells must be processed in a limited time. Yet, the sorting rates of commercial cell sorters are not high enough to reach the required yield. Process parallelization by using multiple instrumen ..read more
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Research Bits: May 21
Semiconductor Engineering
by Jesse Allen
2d ago
Lithium tantalate PICs Researchers at EPFL and Shanghai Institute of Microsystem and Information Technology developed scalable photonic integrated circuits (PICs) based on lithium tantalate (LiTaO3). Lithium tantalate can provide excellent electro-optic qualities and is used in telecom 5G RF filters. The team developed a wafer-bonding method for lithium tantalate, which is compatible with silicon-on-insulator production lines. They then masked the thin-film lithium tantalate wafer with diamond-like carbon and used DUV photolithography and dry-etching techniques to create optical waveguides, mo ..read more
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Chip Industry Technical Paper Roundup: May 21
Semiconductor Engineering
by Linda Christensen
2d ago
New technical papers added to Semiconductor Engineering’s library this week. Technical Paper Research Organizations DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands Seoul National University and University of Illinois at Urbana-Champaign Anomalous isotope effect on the optical bandgap in a monolayer transition metal dichalcogenide semiconductor Oak Ridge National Laboratory (ORNL) and University of Central Florida Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC ETH Zurich ..read more
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DRAM Microarchitectures And Their Impacts On Activate-Induced Bitflips Such As RowHammer 
Semiconductor Engineering
by Technical Paper Link
3d ago
A technical paper titled “DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of Illinois at Urbana-Champaign. Abstract: “The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enhance reliability, and mitigate security vulnerability. Nonetheless, DRAM manufacturers have disclosed only a limited amount of information, making it difficult to find specific information on their DRAM microa ..read more
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Competitive Open-Source EDA Tools
Semiconductor Engineering
by Technical Paper Link
3d ago
A technical paper titled “Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC” was published by researchers at ETH Zurich and University of Bologna. Abstract: “We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (SoC). We present enhancements to synthesis tools and logic optimization scripts improving quality of results (QoR), as well as an optimized physical design with an improved power grid and cell placement integr ..read more
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