Rare-earths deal; top technology megatrends; DDR5 standard; rare earths; chiplet packaging deal; SDV partnership; legacy process nodes; UK-India deal; DRAM, NAND flash revenue The post Chip Industry Week In Review appeared first on Semiconductor Engineering ..read more

The good, bad, and unknowns of AI, and what's missing for design and verification. The post Insights From The AI Hardware & Edge AI Summit appeared first on Semiconductor Engineering ..read more

In today’s rapidly evolving semiconductor design landscape, efficiency and productivity are integral to success. It is here that Integrated Development Environments (IDEs) are making a significant impact. These software suites are much more than programming environments where designers input text or code. They represent a comprehensive ecosystem of tools, utilities, and functionalities, all designed to streamline the development process and catalyze the creation of high-quality code. An IDE, at its core, brings together several essential features such as code introspection, which allows you to ..read more

Experts At The Table: EDA has undergone numerous workflow changes over time. Different skill sets have come into play over the years, and at times this changed the definition of what it means to design at the system level. Semiconductor Engineering sat down to discuss what this means for designers today, and what the impact will be in the future, with Michal Siwinski, chief marketing officer at Arteris; Chris Mueth, new opportunities business manager at Keysight; Neil Hand, director of marketing at Siemens EDA; Dirk Seynhaeve, vice president of business development at Sigasi; and Frank Schirrm ..read more

At DAC this year, there was a lot of talk about AI and the impact it is likely to have. While EDA companies have been using it for optimization and improving iteration loops within the flow, the end users have been concentrating on how to use it to improve the user interface between engineers and tools. The feedback is very positive. Large language models (LLMs) have been trained on a huge amount of data available on the Internet, and they have been shown to be quite good at summarizing and replicating that information in various forms. What they lack is domain specific knowledge about design ..read more

Designing automotive Advanced Driver Assistance Systems (ADAS) applications can be incredibly complex. State-of-the-art ADAS and autonomous driving systems use ‘sensor fusion’ to combine inputs from multiple sources, typically cameras and optionally radar and lidar units to go beyond passive and active safety to automate driving. Vision processing systems combine specialized AI accelerators with general-purpose CPUs and real-time actuation CPUs, sharing data between them where appropriate, incorporating sufficient resilience to achieve the required automotive safety levels. AI/ML approaches to ..read more

By Aakash Jani and Lee Vick Let me set the scene. You are a child psychologist (played by, let’s say, Bruce Willis for illustrative purposes), and you are sitting next to a frightened kid. He turns to you and whispers, “I see dead bits.” Okay, I grant you that’s not exactly the quote, but data center operators are seeing transient errors at an alarming rate, and at scale. These errors are colloquially known as silent data corruption (SDC) and are a serious threat to reliability, availability, and serviceability (RAS) in data centers today, as cited by Meta1, Google2, and Intel3 independently ..read more

By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making it extremely challenging to verify the correctness of the connections. The traditional way to verify these connections requires a lot of manpower and time and is either not exhaustive or too late in the proc ..read more

SystemVerilog constraint randomization is a powerful methodology for generating realistic and diverse test scenarios in the realm of hardware design verification. However, like any complex methodology, it can sometimes be challenging to debug when an unexpected issue arises. In this article, we will explore common debug techniques and strategies to help you effectively troubleshoot your SystemVerilog constraint randomization code. Understand the basics Before delving into debugging, it is critical to have a solid understanding of the basics of SystemVerilog constraint randomization. Constraint ..read more

3D-ICs and heterogeneous chiplets will require significant changes in physical layout tools, where the placement of chiplets and routing of signals can have a big impact on overall system performance and reliability. EDA vendors are well aware of the issues and working on solutions. Top on the list of challenges for 3D-ICs is thermal dissipation. Logic typically generates the most heat, and stacking logic chiplets on top of other logic chiplets requires a way to dissipate that heat. In a planar SoC, this is typically handled through a heat sink or the substrate. But in a 3D-IC, the substrate n ..read more